Interleaver-Based Error Correction Coding for Variable Transmission Speeds
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Solution Overview
Problem
Existing communication devices face challenges in changing error-correction coding speeds without increasing circuit scale and cost when transmission speeds change, such as from 100 Gigabit/sec to 200 Gigabit/sec, due to the need for multiple error correction encoders operating in parallel.
Innovation Solution
The implementation of an encoder and decoder system that generates coded bit sequences based on bits arranged at different intervals in transmission frames, allowing for speed adjustment without requiring additional circuit elements, by using a single series of interleaving memory for both standard and N-times speed modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple error correction encoders are mounted to change execution speed, then the execution speed of error-correction coding can be changed, but the scale of the whole circuit becomes large
Solution Approach 1:
The patent applies dynamics by making the error correction encoder operable at multiple execution speeds through dynamic configuration. The encoder can switch between operating modes (e.g., single-speed, dual-speed) based on transmission requirements, allowing the same hardware to adapt its processing speed without physical reconfiguration or additional dedicated circuits for each speed level.
Solution Approach 2:
The patent implements universality by designing a single error correction encoder that can perform multiple functions at different execution speeds. The encoder is capable of operating in various modes (single-speed mode, dual-speed mode with different speed ratios) using the same hardware resources, eliminating the need for separate encoders for each speed requirement and reducing overall circuit scale.
2Speed
If multiple error correction encoders are mounted to change execution speed, then the execution speed of error-correction coding can be changed, but the cost of the communication device increases
Solution Approach 1:
The patent reduces manufacturing cost by implementing a universal error correction encoder that can operate at multiple execution speeds. Instead of manufacturing separate encoders for different speed requirements, a single multi-functional encoder is produced that can be configured for various transmission speeds, simplifying the manufacturing process and reducing device cost.
Solution Approach 2:
The patent changes operational parameters (execution speed, speed ratio) of the error correction encoder without changing the hardware configuration. By adjusting control parameters and operating modes rather than physical components, the system achieves variable execution speeds while maintaining consistent manufacturing costs and device architecture.
3Speed
If the circuit is designed to change execution speed, then the execution speed can be adjusted, but temporary storage capacity increases
Solution Approach 1:
The patent applies dynamics by implementing temporary storage capacity that adapts to execution speed requirements. The storage resources are dynamically allocated and sized according to the operating mode and speed ratio, allowing efficient use of memory without over-provisioning for maximum speed scenarios. The system adjusts storage usage patterns based on current execution speed demands.
Data Source
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AI summary
An error correction encoder (10) includes an interleaver circuit (31), encoding circuits (321, 322) and a deinterleaver circuit (33). The interleaver circuit (31) generates, in a standard speed mode, a single series of yet-to-be-coded bit sequences (IL1) on the basis of the bits in plural columns that are arranged at an interval of C columns in a single series of transmission frames, and generates, in a two-times speed mode, two series of yet-to-be-coded bit sequences (IL1, IL2) on the basis of the bits in plural columns that are arranged at an interval of C/2 columns in each of two series of transmission frames. The encoding circuits (321, 322) apply error-correction coding to either the single series of yet-to-be-coded bit sequences (IL1) or the two series of yet-to-be-coded bit sequences (IL1, IL2).