Convolutional Interleaver Memory Layout for Higher DMA Throughput
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Solution Overview
Problem
Existing convolutional interleavers and deinterleavers that employ direct memory access (DMA) controllers for external memory access face inefficiencies in data throughput due to wastage of bandwidth and high discard rates of unnecessary bytes during DMA read accesses.
Innovation Solution
The implementation of a convolutional interleaver or deinterleaver that utilizes both external memory accessed via a DMA controller and a cache memory, where the cache memory is used to store bytes forming output words, optimizing DMA transfer efficiency by maximizing the number of bytes read during burst mode accesses and reducing discard rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DMA controller is used for external memory access in convolutional interleaver/deinterleaver, then data storage capacity is improved, but data throughput deteriorates due to bandwidth wastage and high discard rates
Solution Approach 1:
The patent divides the memory system into two segments: external memory for bulk data storage and an internal buffer for active data manipulation. This segmentation allows the DMA controller to efficiently manage large storage capacity while the buffer handles high-speed data transfer operations, resolving the contradiction between storage capacity and throughput.
Solution Approach 2:
The internal buffer acts as an intermediary between the external memory and the interleaver/deinterleaver logic. It receives data from external memory via DMA, prepares it for processing, and supplies data to the output, thereby eliminating the direct bottleneck between DMA controller and processing logic, improving overall throughput.
2Productivity
If external memory is accessed via DMA controller in burst mode, then memory access efficiency is improved, but unnecessary bytes are discarded due to mismatch between burst length and required data
Solution Approach 1:
The patent performs preliminary action by pre-fetching data blocks into the internal buffer before they are needed for interleaving/deinterleaving operations. This allows the system to prepare data in advance, ensuring that when data is needed, it is already available in the buffer without requiring partial discards from external memory bursts.
Solution Approach 2:
The system dynamically adjusts the buffer size and DMA transfer parameters to match the specific interleaving depth and word length requirements. By changing these parameters, the system optimizes the burst length to closely match the actual data requirements, minimizing discarded bytes while maintaining high memory access efficiency.
3Reliability
If interleaving depth is increased to improve noise immunity, then noise immunity is improved, but memory storage requirements increase
Solution Approach 1:
The patent introduces a temporal dimension to the memory architecture by using the internal buffer to hold data temporarily during processing. This allows the system to achieve high interleaving depths (which normally require proportionally large memory) by cycling data through the buffer multiple times, effectively trading time for space and reducing overall memory requirements while maintaining noise immunity.
Data Source
AI summary
An apparatus for receiving and storing an incoming sequence and for forwarding the bytes of the incoming sequence as an outgoing sequence in a different byte order includes a cache memory and a main memory for storing bytes of the incoming sequence until they can be forwarded as bytes of the outgoing sequence. A control circuit selectively burst mode writes sequences of incoming bytes that need be stored for a relatively long time to blocks of sequential addresses of the main memory, writes individual bytes of the incoming sequence that need be stored for a relatively short time to selected addresses of the cache memory, and reads bytes out of the cache memory and the main memory when needed to form the outgoing sequence.