Line-Rate Interleaver Memory Mapping for Low-Latency Throughput
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing deinterleaver devices in wireless communications systems, particularly in satellite communications, face latency issues due to multiple RAM operations and require significant memory and hardware to maintain throughput, especially at high line rates like 3.8 Gbps and above.
Innovation Solution
A method and device for deinterleaving and interleaving data that reduces memory and hardware requirements by virtually dividing memory into sections based on stream counts, calculating write addresses for correct deinterleaving or interleaving locations, and writing samples sequentially without latency, supporting various modulation schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple RAMs and parallel deinterleaving chains are used to maintain throughput, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent divides the deinterleaving process into multiple parallel chains, where each chain processes a portion of the data stream. This segmentation allows the system to maintain high throughput by distributing the processing load across multiple independent units, while each unit remains relatively simple in structure.
Solution Approach 2:
The patent combines multiple deinterleaving chains into a single integrated system that processes data in parallel. By merging the functionality of multiple chains under a unified control structure, the system achieves high throughput without proportionally increasing overall device complexity.
2Productivity
If multiple RAM operations are performed to deinterleave data, then productivity is improved, but loss of time increases
Solution Approach 1:
The patent performs preliminary organization of data into parallel chains before the actual deinterleaving operation. By pre-processing and structuring the data stream into manageable segments, the system reduces the number of sequential RAM operations needed during the main deinterleaving process, thereby reducing latency while maintaining throughput.
Solution Approach 2:
The patent implements continuous parallel processing across multiple deinterleaving chains, eliminating idle time and sequential waiting periods. Data flows continuously through the parallel chains without interruption, maintaining high throughput while minimizing the total time required for deinterleaving operations.
3Productivity
If multiple RAMs are used to buffer data, then productivity is improved, but quantity of substance increases
Solution Approach 1:
The patent segments the data buffer into multiple smaller memory units distributed across parallel deinterleaving chains. Instead of using one large memory block, each chain uses a smaller local buffer, reducing the total memory requirement while maintaining the ability to handle high throughput through parallel access.
Solution Approach 2:
The patent transitions from a single-dimension sequential memory access model to a multi-dimensional parallel memory structure. By organizing memory access across multiple parallel chains simultaneously, the system achieves high throughput with reduced total memory capacity, effectively adding a parallelism dimension to the memory architecture.
Data Source
AI summary
A deinterleaver device, a method for deinterleaving, an interleaver device, and a method for interleaving are provided. The method for deinterleaving includes: providing a memory and a stream count for a frame; virtually dividing the memory into equal sections, wherein a section count equals the stream count; calculating a write address for a sample of the samples based on a location of the sample in the frame and a correspondence of the location to one of the sections; receiving the sample; and writing the received sample to the write address, wherein the calculating and the write address corresponds to a correct deinterleaving location in one of the sections for the sample.