High-Speed Interleaver Memory Segmentation for Line-Rate Throughput

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Solution Overview

Problem

Existing deinterleaver devices in wireless communications systems, particularly in satellite communications, face latency issues due to multiple RAM operations and require significant memory and hardware to maintain high throughput across various modulation schemes.

Innovation Solution

A deinterleaver device that operates by virtually dividing memory into sections based on stream count, calculating and writing sample addresses to correct deinterleaving locations, reducing memory and hardware requirements while maintaining high throughput and eliminating latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple RAMs and parallel deinterleaving chains are used to maintain high throughput, then productivity is improved, but device complexity increases

Engineering Contradiction:
ImprovethroughputVSAvoidhardware complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory is virtually divided into multiple sections corresponding to different streams, allowing parallel processing of multiple deinterleaving operations within a single RAM structure. This segmentation enables high throughput by processing multiple streams simultaneously while avoiding the need for multiple separate RAM devices, thus reducing hardware complexity.

Inventive Principle:
Principle #1Segmentation

2Productivity

If multiple RAM operations are performed to achieve deinterleaving, then productivity is improved, but loss of time increases

Engineering Contradiction:
ImprovethroughputVSAvoidlatency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The deinterleaving addresses are calculated and prepared in advance for each incoming sample. By pre-calculating the write address for each section based on the stream count and sample position, the system eliminates the need for multiple sequential RAM operations, thereby reducing latency while maintaining high throughput.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If multiple input and output RAMs are used to buffer data, then productivity is improved, but device complexity increases

Engineering Contradiction:
ImprovethroughputVSAvoidmemory quantity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

A single RAM is designed to perform multiple functions by virtually dividing it into multiple sections, each handling different streams. This multi-functional approach allows one RAM to replace what would traditionally require multiple separate RAM devices, reducing the overall memory quantity while maintaining the ability to handle multiple streams in parallel for high throughput.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10819469B2High speed interleaver/deinterleaver device supporting line rate, and method thereof
Publication Date: 2020.10.27 HUGHES NETWORK SYST
  • US10819469B2 patent drawing
  • US10819469B2 patent drawing
  • US10819469B2 patent drawing

AI summary

A deinterleaver device, a method for deinterleaving, an interleaver device, and a method for interleaving are disclosed. The method for deinterleaving includes: providing a memory and a stream count for a frame; virtually dividing the memory into equal sections, wherein a section count equals the stream count; calculating a write address for a sample of the samples based on a location of the sample in the frame and a correspondence of the location to one of the sections; receiving the sample; and writing the received sample to the write address, wherein the calculating and the write address corresponds to a correct deinterleaving location in one of the sections for the sample.