Parallel Interleaver Memory Routing to Avoid Write Conflicts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In turbo decoders, the restructured interleavers and deinterleavers face write conflicts due to serial memory access limitations when attempting to process and reformat data in parallel, hindering the data throughput enhancement efforts.
Innovation Solution
The implementation of a system using a plurality of interleavers and deinterleavers with First-In-First-Out (FIFO) buffers and routers to direct data items into respective segments, avoiding write conflicts by serially routing data items into memory, and utilizing demultiplexers and multiplexers to manage data distribution and assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel processing is introduced to increase data throughput, then processing speed is improved, but memory write conflicts occur due to serial access limitations
Solution Approach 1:
The patent segments the interleaver and deinterleaver into multiple parallel processing units (first interleaver, second interleaver, first deinterleaver, second deinterleaver). Each unit processes a separate portion of the data block simultaneously, enabling parallel operation while maintaining serial memory access through dedicated memory ports for each unit. This segmentation allows throughput improvement without causing memory conflicts.
Solution Approach 2:
The patent introduces intermediate buffers between the parallel processing units and the serial memory access interface. These buffers act as intermediaries that decouple the parallel processing operations from the serial memory write operations, allowing multiple processors to write to memory simultaneously through buffered intermediate storage, thus preventing write conflicts while maintaining high throughput.
2Productivity
If restructured interleavers are used for parallel processing, then processing efficiency is improved, but write conflicts arise due to serial memory access
Solution Approach 1:
The interleaver is restructured into multiple independent interleaving units that each handle a specific segment of the data. This segmentation allows each unit to operate in parallel without interfering with others, maintaining processing efficiency while eliminating write conflicts through dedicated memory access paths for each segment.
Solution Approach 2:
Each parallel processing unit is assigned dedicated local resources including its own memory port and buffer memory. This local quality assignment ensures that each unit has exclusive access to its designated resources, preventing write conflicts while maintaining high processing efficiency through parallel operation of locally-optimized units.
3Productivity
If faster hardware is used to increase throughput, then data throughput is improved, but system complexity increases
Solution Approach 1:
Instead of using a single high-speed hardware unit, the patent segments the processing into multiple lower-speed units operating in parallel. This segmentation achieves the same throughput improvement without requiring extremely fast hardware, thereby reducing individual component complexity while maintaining overall system productivity through coordinated parallel operation.
Data Source
AI summary
Interleaving and deinterleaving schemes for operating in parallel on sections of a data block to load memories with respective segments of a reordered version of the block, in a manner which can avoid memory conflicts.