Interleaver Quotient-Remainder Reordering for Low-Complexity Encoding
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Solution Overview
Problem
Existing interleavers in turbo encoders require complex and resource-intensive logic for calculating interleaver sequence functions, leading to increased circuit complexity, size, and power consumption, particularly in mobile applications.
Innovation Solution
The interleaver sequence function is expressed in quotient and remainder form, allowing for simplified calculations using lookup operations and iterative shift-add operations, reducing the need for complex divider logic and minimizing processing overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional interleaver sequence function calculation is used, then accurate interleaving is achieved, but circuit complexity and processing overhead increase
Solution Approach 1:
The interleaver sequence function calculation is segmented into two distinct stages: a preprocessing stage that generates and stores lookup tables containing pre-computed interleaver sequence values, and a processing stage that simply retrieves values from these tables during actual interleaving operations. This segmentation transforms the complex real-time calculation into simple table lookups, resolving the contradiction between accuracy and complexity.
Solution Approach 2:
The lookup tables are prepared in advance during system initialization or preprocessing, storing pre-computed interleaver sequence values for all possible input positions. By performing the complex calculation work beforehand, the actual interleaving process only requires simple memory retrieval operations, thereby maintaining accuracy while dramatically reducing processing overhead and circuit complexity.
2Measurement precision
If complex divider logic is implemented for interleaver calculation, then precise interleaver sequence is obtained, but processing time and power consumption increase
Solution Approach 1:
The computationally intensive division operations required for precise interleaver sequence calculation are performed in advance during lookup table generation. The pre-computed results are stored in memory, allowing the actual interleaving process to use simple memory read operations instead of time-consuming division calculations, thus maintaining precision while reducing processing time.
Solution Approach 2:
Instead of performing complex calculations during real-time processing, the patent creates copies of the interleaver sequence values in lookup tables. These copied values can be retrieved instantly without reperforming the complex mathematical operations, thereby maintaining precision while significantly reducing processing time and power consumption.
3Manufacturing precision
If full precision calculation is performed, then accurate interleaved bit locations are determined, but hardware resources and computation time increase
Solution Approach 1:
The calculation process is segmented into offline table generation (where full precision is computationally expensive but acceptable) and online table lookup (where only memory access is needed). This segmentation allows accurate bit location determination while minimizing hardware resources during actual operation, as the complex computation is performed once during table generation rather than continuously during processing.
Data Source
AI summary
A method of generating an interleaved symbol sequence location from a symbol location of a symbol sequence comprises determining the interleaved symbol location based on an interleaver sequence function which relates a linear symbol location to the interleaved symbol location. This is done by acquiring values of the interleaver sequence function in quotient and remainder form and then calculating the interleaved symbol location by performing operations of the interleaver sequence function in quotient and remainder form.