Interleaving Apparatus Buffer Segmentation for NAND Flash

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Solution Overview

Problem

Conventional interleaving apparatuses for NAND flash memory devices have complex structures and are inefficient in performing interleaving operations, making them unsuitable for small form factors and varying operation modes.

Innovation Solution

A simplified interleaving apparatus with a first buffer unit for sectoring data, an encoding unit for generating parity codes, and a second buffer unit for interleaving sector unit data and parity codes, allowing for flexible interleaving operations and reduced buffer sizes, integrated into a memory controller for efficient write and read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional interleaving apparatuses are used, then interleaving operations can be performed, but the structure becomes complicated and the size increases

Engineering Contradiction:
Improveinterleaving operation efficiencyVSAvoidapparatus structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The interleaving apparatus is divided into multiple buffer units (first buffer unit, second buffer unit) and processing units (encoding unit, output unit). Each buffer unit handles specific tasks such as sectoring data, generating parity codes, or performing interleaving operations. This segmentation allows the system to achieve efficient interleaving operations while maintaining a manageable and simplified overall structure, as each segment can be optimized independently for its specific function.

Inventive Principle:
Principle #1Segmentation

2Productivity

If conventional interleaving apparatuses are used, then interleaving operations can be performed, but the buffer sizes become large

Engineering Contradiction:
Improveinterleaving operation efficiencyVSAvoidbuffer size
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The buffer units are configured with flexible sizes that can be dynamically adjusted based on the specific interleaving operation requirements. The first buffer unit buffers input data in units having a size of a sector, while the second buffer unit performs interleaving operations with configurable buffer sizes. This dynamic configuration allows the system to reduce buffer sizes when performing simpler interleaving operations while maintaining the capability to handle complex operations when necessary, thus optimizing the balance between productivity and resource consumption.

Inventive Principle:
Principle #15Dynamics

3Productivity

If conventional interleaving apparatuses are used, then interleaving operations can be performed, but the adaptability to various operation modes is limited

Engineering Contradiction:
Improveinterleaving operation efficiencyVSAvoidoperation mode flexibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The interleaving apparatus is designed with multi-functional buffer units and processing units that can adapt to various operation modes. The first buffer unit can buffer data for different sector sizes, the encoding unit can generate parity codes for different error correction requirements, and the second buffer unit can perform interleaving operations with different patterns. This universality allows the same apparatus to efficiently perform interleaving operations in various modes (e.g., different interleaving depths, data grouping configurations) without requiring separate dedicated hardware for each mode, thus improving both productivity and adaptability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8812942B2Interleaving apparatuses and memory controllers having the same
Publication Date: 2014.08.19 SAMSUNG ELECTRONICS CO LTD
  • US8812942B2 patent drawing
  • US8812942B2 patent drawing
  • US8812942B2 patent drawing

AI summary

An interleaving apparatus may include a first buffer unit configured to buffer input data in units having a size of a sector to generate sector unit data, an encoding unit configured to encode the sector unit data and generate a plurality of parity codes based on the encoding, a second buffer unit configured to interleave the sector unit data and the parity codes and generate interleaving data based on the interleaving, the second buffer unit including a plurality of output buffers configured to store the interleaving data, and an output unit configured to output the interleaving data.