Interleaving Memory Addressing for Cyclic Readout Without Extra Memory
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Solution Overview
Problem
Existing interleaving methods require additional memories and reduce processing speed due to the need for cyclic interleaving, which is not efficiently addressed by conventional symbol, tone, and cyclic interleaving techniques.
Innovation Solution
A method and system that perform cyclic interleaving without additional memories by mathematically determining the order of reading data from symbol-interleaved banks using a predetermined read address value calculation process, incorporating tone and cyclic interleaving values to optimize data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional symbol, tone, and cyclic interleaving techniques are used, then data transmission reliability is improved, but additional memories are required and processing speed is reduced
Solution Approach 1:
The patent extracts the cyclic interleaving function from separate memory structures and integrates it into the existing symbol interleaver architecture. By reusing the same memory resources for both symbol and cyclic interleaving operations through mathematical address mapping, the need for additional dedicated memory is eliminated while maintaining the reliability benefits of cyclic interleaving.
Solution Approach 2:
The patent makes the memory structure universal by enabling it to perform both symbol interleaving and cyclic interleaving functions. Through the use of mathematical address calculation formulas that incorporate both symbol interleaving parameters (N, M) and cyclic interleaving parameters (Q), the same memory can execute multiple interleaving operations without requiring separate dedicated memory structures for each function.
2Reliability
If conventional symbol, tone, and cyclic interleving techniques are used, then data transmission reliability is improved, but processing speed is reduced
Solution Approach 1:
The patent extracts the cyclic interleaving operation from a separate processing stage and integrates it into the symbol interleaving process. By combining both operations into a single unified memory access sequence with mathematically derived address patterns, the processing pipeline is streamlined and unnecessary sequential processing steps are eliminated, thereby improving processing speed while maintaining reliability.
Solution Approach 2:
The patent merges symbol interleaving and cyclic interleaving into a single unified operation. Through the integration of both interleaving functions within one memory access sequence using combined address mapping formulas, the processing overhead of separate operations is eliminated, resulting in improved processing speed while preserving the error distribution benefits of both interleaving techniques.
3Reliability
If additional memories are allocated for cyclic interleving, then data transmission integrity is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the cyclic interleaving function from separate memory allocations and reimplements it through software-based address mapping. By using mathematical formulas to calculate read addresses that incorporate cyclic interleaving patterns, the need for additional physical memory structures is removed, reducing device complexity and cost while maintaining data transmission integrity through the same interleaving effect.
Solution Approach 2:
The patent replaces the mechanical/physical approach of allocating separate memory structures for cyclic interleaving with a computational/software-based approach. By using address calculation algorithms that mathematically implement cyclic interleaving patterns on existing memory, the physical complexity of the memory system is reduced while the logical function of cyclic interleaving is preserved, thereby maintaining integrity without increasing device complexity.
Data Source
AI summary
An interleaving method employing symbol interleaving, tone interleaving, and cyclic interleaving for transmitting data includes storing data at write address values in a memory which are sequentially calculated according to a predetermined process, and reading data stored at read address values of the memory which are sequentially calculated according to a predetermined process, wherein the memory has N data banks, each data bank has M storage spaces, and there are D interleaving target data having data numbers A, and the storing data operation includes storing the data at storage spaces of the data banks, the storage spaces corresponding to integer values and the data banks corresponding to remainders obtained by dividing the data numbers A by results of dividing a total number of data D by the number of storage spaces M.