Interlevel Connectors in 3D Memory Arrays
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Solution Overview
Problem
Existing 3D stacked memory devices and circuit structures face challenges with a high number of lithographic and etch mask steps, as well as a large area requirement for contact structures, including interlevel connectors, which increase costs and reduce density, especially as the number of levels increases.
Innovation Solution
The implementation of an etch-trim process to form a reduced number of steps in contact regions, combined with anisotropic step etch processes, allows for interlevel connectors to be formed with a smaller area requirement and fewer photomask steps, using a configuration where each contact region has landing areas on subsets of levels, reducing the overall area and number of steps needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional stairstep structures are formed to accommodate interconnects in 3D stacked memory devices, then vertical interlevel connections can be made to landing areas on each level, but a high number of lithographic and etch mask steps are required
Solution Approach 1:
The patent segments the contact regions into multiple discrete locations around the perimeter of the 3D memory array, with each contact region providing access to a specific subset of levels. This segmentation allows different etch-trim cycles to target specific contact regions, reducing the overall number of mask steps required compared to forming all contacts in a single monolithic structure.
Solution Approach 2:
The patent applies preliminary etch-trim cycles to selected contact regions before completing the formation of all contact structures. By performing etching and trimming operations in advance on specific contact regions, the process reduces the total number of subsequent mask steps needed to complete all interlevel connectors.
2Reliability
If traditional stairstep structures are formed to accommodate interconnects in 3D stacked memory devices, then vertical interlevel connections can be made to landing areas on each level, but a relatively large area in layout is required
Solution Approach 1:
The patent implements local quality by providing different contact region configurations at different locations around the perimeter of the 3D memory array. Each contact region is optimized for its specific position and targets a specific subset of levels, allowing for more efficient space utilization and reduced overall area compared to uniform stairstep structures.
Solution Approach 2:
The patent transitions from traditional two-dimensional planar contact layouts to a three-dimensional arrangement where contact regions are distributed around the perimeter of the stacked array at multiple vertical levels. This dimensional change allows interlevel connectors to access landing areas more efficiently, reducing the footprint area required for contact structures.
3Quantity of substance
If the number of levels increases for high density circuits, then storage density increases, but the number of lithographic and etch mask steps increases and area requirements increase
Solution Approach 1:
The patent segments the access to W levels across N contact regions, with each contact region providing access to a specific subset of levels. This segmentation allows the formation of interlevel connectors to be divided into multiple targeted etch-trim cycles rather than requiring a single comprehensive process, reducing the overall number of mask steps even as the total number of levels increases.
Solution Approach 2:
The patent applies partial action by having each contact region target only the specific subset of levels it needs to access, rather than forming all possible contacts at all levels. This approach reduces the total number of etch-trim cycles required while still providing complete access to all W levels across the N contact regions.
4Quantity of substance
If the number of levels increases for high density circuits, then storage density increases, but the area required for contact structures increases
Solution Approach 1:
The patent utilizes three-dimensional space by distributing contact regions around the perimeter of the stacked array at multiple vertical levels, rather than confining all contacts to a single planar layer. This dimensional approach allows efficient access to W levels across N contact regions, reducing the footprint area required even as storage density increases with more levels.
Data Source
AI summary
Multilevel circuitry such as a a 3D memory array, has a set of contact regions arranged around a perimeter of a multilevel region, in which connection is made to circuit elements in a number W levels. Each of the contact regions has a number of steps having landing areas thereon, including steps on up to a number M levels, where the number M can be much less than W. A combination of contact regions provides landing areas on all of the W levels, each of the contact regions in the combination having landing areas on different subsets of the W levels. A method of forming the device uses an etch-trim process to form M levels in all of the contact regions, and one or more anisotropic etches in some of the contact regions.