Interlock Circuit Dead-Time Logic for Shoot-Through Prevention
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Solution Overview
Problem
Existing interlock circuits fail to effectively manage simultaneous input signals, leading to output signal errors and potential circuit damage due to simultaneous enablement of output signals, which can cause shoot-through conditions and instability in high-voltage systems.
Innovation Solution
An interlock circuit with an input delay unit and an output suppressing unit that delays and performs logical operations on input signals to generate exclusive input signals, preventing simultaneous enablement of output signals by inserting a predetermined dead time after one output signal is disabled, ensuring a first-in first-out operation and reducing output signal errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If input signals are directly processed without delay, then response speed is improved, but simultaneous enablement of multiple output signals occurs causing shoot-through conditions
Solution Approach 1:
The patent applies preliminary action by introducing delay units that pre-process input signals before they reach the output stage. The first delay unit delays the first input signal, and the second delay unit delays the second input signal, ensuring that even if both inputs arrive simultaneously, their processed versions are staggered in time, preventing simultaneous output enablement and shoot-through conditions.
Solution Approach 2:
The patent uses delay units as intermediary elements between the input signals and the output stage. These delay units act as mediators that temporarily hold and sequentially release the input signals, ensuring that the output signals are never enabled simultaneously. This intermediary mechanism resolves the contradiction by adding temporal separation without significantly impacting the overall system response.
2Reliability
If delay units are added to prevent simultaneous output signals, then circuit stability is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the interlock circuit into distinct functional modules: delay units, logical operation units, and output stage. Each delay unit processes one input signal independently, and each logical operation unit handles specific logic functions. This modular segmentation makes the circuit easier to design, analyze, and manufacture despite the added complexity of multiple components.
3Measurement precision
If logical operation units are added to generate exclusive input signals, then output signal accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies merging by combining the delay units and logical operation units into an integrated signal processing path. The delayed input signals are fed into logical operation units that perform AND, OR, and NOT operations to generate exclusive input signals. This merging of functions ensures accurate output signal generation while optimizing the circuit layout to minimize overall complexity.
Data Source
AI summary
An interlock circuit includes an input delay unit and an output suppressing unit. The input delay unit delays a plurality of input signals, provides a plurality of delayed input signals, and provides a plurality of exclusive input signals by performing a logical operation on the plurality of delayed input signals. The output suppressing unit provides a plurality of output signals, which are not simultaneously enabled, based on the plurality of exclusive input signals and the plurality of input signals.