Interlocking Data Conversion Using Dual Translators for Formal Verification

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Solution Overview

Problem

The complexity and scale of interlocking systems in rail traffic signal systems make it challenging to verify interlocking data thoroughly, leading to potential safety risks due to untested data channels and increased design defects.

Innovation Solution

A method involving two translators developed in different programming languages to convert interlocking data into formats recognizable by formal verification tools, ensuring consistency and safety through comparison of output files.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional test verification process by manual test is used, then ease of operation is maintained, but measurement precision and reliability of interlocking data verification deteriorate due to inability to cover all application scenes and potential mistaken data channels

Engineering Contradiction:
Improveverification coverageVSAvoidverification system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent replaces manual mechanical testing with automated formal verification methods. The formal verification tool automatically analyzes interlocking data against safety specifications, eliminating the need for manual test case design and execution while achieving complete coverage of all possible application scenes and data channels.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent creates formal models that are precise copies or representations of the actual interlocking system behavior. These formal models include interlocking objects, safety specifications, and test scenarios that mirror the real system, allowing exhaustive verification without physical testing.

Inventive Principle:
Principle #26Copying

2Reliability

If formal verification is applied to each specific station, then reliability and measurement precision improve, but device complexity and technical cost increase significantly

Engineering Contradiction:
Improveinterlocking data safetyVSAvoidformal development complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent develops a universal formal verification framework that can be applied to any interlocking station regardless of specific configuration. The safety specifications and verification methods are designed to be station-agnostic, allowing the same formal verification tool and process to verify interlocking data across multiple different stations without requiring custom development for each station.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If interlocking system complexity increases to meet functional requirements, then adaptability and versatility improve, but difficulty of detecting and measuring errors increases

Engineering Contradiction:
Improveinterlocking function coverageVSAvoiddata verification difficulty
Core Design Contradiction:
Adaptability or versatilityVSDifficulty of detecting and measuring

Solution Approach 1:

The formal verification process provides automatic feedback on whether interlocking data satisfies safety specifications. The verification tool analyzes the formal models and generates verification results that indicate whether the interlocking logic meets safety requirements, making error detection systematic and automated rather than manual and difficult.

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP4095676B1Safe interlocking data conversion method for formal verification and translator
Publication Date: 2025.08.13 CASCO SIGNAL LTD
  • EP4095676B1 patent drawingFigure 1
  • EP4095676B1 patent drawingFigure 2
  • EP4095676B1 patent drawingFigure 3

AI summary

Disclosed are an interlocking data safe conversion method for formal verification and a translator. Two translators with same functions are developed by adopting different programming methods and programming languages. An input file of each of the translators at least comprises an interlocking information table in interlocking data, a device interface information table, a station yard description data and interlocking Boolean logic data. Consistency of output files of the two translators is compared to realize detection process failure, so that safe conversion of data is guaranteed. It is unnecessary to perform specific formal development for each station, so that the technical cost and the design risk are reduced, and the present invention is high in safety, good in compatibility, high in universality and wide in application range.