Micro Interconnect Structures Using Interlocking Die Sidewalls
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing the dedicated edge space required for interconnects, which limits the active die area and increases the overall footprint of semiconductor packages.
Innovation Solution
The method involves forming inter-die interconnects between semiconductor die with contacting side surfaces, using conductive layers and precision plasma etching to create extensions and recesses on the side surfaces, allowing for direct physical contact and minimal electrical interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional wire bonding methods are used for inter-die interconnect, then electrical connection is achieved, but dedicated edge space and separation distance are required, reducing active die area and increasing package footprint
Solution Approach 1:
The patent merges the interconnect function directly into the die side surfaces by forming conductive layers and interlocking features (extensions and recesses) on the die edges. This eliminates the need for separate wire bonds and dedicated edge space, allowing the interconnect structure to be integrated within the die footprint itself, thereby maximizing active die area while maintaining electrical connection functionality
Solution Approach 2:
The patent transitions from planar wire bonding (2D approach requiring edge space) to a 3D interlocking structure where conductive layers are formed vertically on die side surfaces. The extensions and recesses create vertical interconnect paths that eliminate the need for lateral separation distance, effectively utilizing the third dimension to resolve the space conflict
2Area of stationary object
If die stacking is used to minimize package footprint, then space efficiency is improved, but heat dissipation and excessive stress become problems particularly for power MOSFETs
Solution Approach 1:
The patent segments the interconnect approach by providing separate interconnection solutions for different die types: side-surface interlocking for standard die and wire bonding for power MOSFET die. This segmentation allows power devices to maintain adequate thermal management while still achieving compact packaging through the new interlocking method for other components
3Length of moving object
If through silicon vias (TSVs) are used for inter-die interconnect, then direct electrical connection is achieved, but manufacturing cost increases
Solution Approach 1:
The patent applies local quality by forming conductive layers only on the specific regions of the die side surfaces where interlocking is needed, rather than creating through-silicon vias that require extensive material removal and filling throughout the entire die thickness. This localized approach achieves direct electrical connection with significantly reduced manufacturing complexity and cost
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the semiconductor package dimensions and cost, increases the efficiency of the footprint, and provides low inductance and resistance compared to traditional wire bonding methods.
Implementation Method 1
precision plasma etching to create extensions and recesses on the side surfaces
Data Source
AI summary
A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.