Rail Interlocking System Heterogeneous Compiler Redundancy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current rail transit interlocking systems face challenges with clock-level synchronization, leading to limitations in CPU performance and inability to handle different algorithms, resulting in common-mode failures and high development and maintenance complexities.
Innovation Solution
A computer-based interlocking system utilizing heterogeneous software/hardware with fixed differences in program running times and a dual 2-vote-2 structure, where CPUs run different compilers to reduce common-mode failures and improve system security, development efficiency, and maintenance requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock-level synchronization is adopted between dual CPUs, then data consistency is ensured, but CPU performance is limited and common-mode failures cannot be eliminated
Solution Approach 1:
The patent applies asymmetry by using different compilers (one strong, one weak) to compile the same source code on dual CPUs. This asymmetric compilation approach allows the strong compiler to optimize for performance while the weak compiler provides a conservative implementation, eliminating the need for strict clock-level synchronization and enabling higher CPU performance without sacrificing data consistency.
Solution Approach 2:
The patent changes the synchronization parameter from strict clock-level timing to compiler-based optimization levels. By adjusting compiler parameters (strong vs. weak optimization) rather than CPU clock frequencies, the system achieves both high performance and data consistency through parameter transformation rather than direct temporal control.
2Stability of the object's composition
If dual CPUs run the same software with clock synchronization, then system stability is maintained, but common-mode software failures cannot be eliminated
Solution Approach 1:
The patent introduces asymmetry in software compilation by using different compilers for the two CPUs. The strong compiler generates highly optimized code while the weak compiler produces conservative code, creating deliberate differences that prevent common-mode software failures while maintaining system stability through comparative verification of results.
Solution Approach 2:
The patent uses copying by having the weak compiler create a conservative copy of the software implementation, which then serves as a reference for verifying the strong compiler's output. This copying approach allows validation of the optimized implementation against a known-good reference, maintaining stability while enabling performance optimization.
3Reliability
If heterogeneous software and hardware are adopted, then common-mode failures are reduced, but development difficulty and maintenance requirements increase
Solution Approach 1:
The patent applies local quality by introducing heterogeneity only in the compilation process (local to the software generation stage) rather than in the entire software-hardware stack. The source code remains the same, and only the compilation parameters differ, which reduces development complexity compared to full heterogeneous systems while still achieving common-mode failure resistance.
Solution Approach 2:
The patent achieves universality by using the same source code for both CPUs, allowing a single codebase to serve multiple purposes (both strong and weak compilation targets). This multi-functional approach to code reuse reduces development and maintenance complexity while the different compilation outcomes provide the necessary heterogeneity for fault tolerance.
4Productivity
If different compilers are used on the same hardware, then common-mode failures are reduced and development efficiency is improved, but system complexity increases
Solution Approach 1:
The patent merges the strong and weak compiler implementations into a unified system architecture where both compilers process the same source code and their results are compared. This merging approach consolidates the complexity management, allowing the system to benefit from both compilation approaches while handling the increased complexity through a structured integration framework.
Data Source
Figure 1
Figure 2~3
Figure 4
AI summary
Disclosed is a computer-based interlocking system and a redundancy switching method based on the interlocking system. The computer-based interlocking system includes an interlocking subsystem; the interlocking subsystem includes an interlocking system I and an interlocking system II that are the same and are connected to each other; wherein each of the interlocking system I and the interlocking system II comprises two CPUs having the same hardware and adopting task-level synchronization; the two CPUs respectively run executable files generated by different compilers through compiling the same program codes. The system adopts heterogeneous software/hardware and program running starting times with a fixed difference to reduce the probability of occurrence of common-mode failures; thus, the development difficulty is lowered, the production efficiency is improved, and requirements for debugging and maintenance are lowered while reducing common-mode failures.