Intermediary Controller Reduces SSD Pad Count
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Solution Overview
Problem
The size of the SSD controller is determined by the number of pads, which increases with the quantity of flash memories, making it challenging to reduce the controller's size effectively.
Innovation Solution
Implementing an intermediary controller with a higher frequency second clock domain, connected between the flash memories and the SSD controller, reduces the number of pads and die size by optimizing data transmission through customized interfaces and data buffering units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the quantity of flash memories increases to improve storage capacity, then the storage capacity is improved, but the quantity of pads increases and the die size of the SSD controller increases
Solution Approach 1:
An intermediary controller is introduced between the flash memories and the SSD controller. This intermediary controller aggregates data from multiple flash memories and transmits it to the SSD controller through a single interface, thereby reducing the number of pads required on the SSD controller while maintaining the ability to access multiple flash memories.
Solution Approach 2:
The control function is segmented between the SSD controller and the intermediary controller. The intermediary controller handles low-level data aggregation and transmission tasks, allowing the SSD controller to focus on higher-level control operations. This segmentation enables the SSD controller to have fewer pads while still managing multiple flash memories effectively.
2Speed
If the frequency of the second clock domain is increased to improve data transmission speed, then the data transmission speed is improved, but the complexity of clock domain management increases
Solution Approach 1:
The system employs dynamic clock domain management where the intermediary controller adapts its internal clock frequencies based on operational requirements. The first clock domain operates at a lower frequency for stable data reception from flash memories, while the second clock domain operates at a higher frequency for rapid data transmission to the SSD controller, with the system dynamically managing the data flow between these domains.
Data Source
AI summary
A solid state disk, a data transmitting method and an intermediary controller thereof are provided. The solid state disk includes at least two flash memories, a SSD controller and an intermediary controller. The intermediary controller is connected between the flash memories and the SSD controller. The intermediary controller includes at least two flash interfaces, a customized interface and a data buffering unit. The flash interfaces are connected to the flash memories. The customized interface is connected to the SSD controller. The intermediary controller has a first clock domain and a second clock domain. The first clock domain is used for transmitting data from the flash memories to the data buffering unit. The second clock domain is used for transmitting data from the data buffering unit to the SSD controller. A frequency of the second clock domain is higher than a frequency of the first clock domain.