Intermediate Bitstream Decoding for Real-Time H.264 Display
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current decoding-processing apparatuses for bitstreams encoded in the H.264 standard face challenges in achieving real-time image display due to serial processing of arithmetic decoding and context calculations, leading to high clock frequencies that are difficult to design and result in errors and poor image quality.
Innovation Solution
A decoding-processing apparatus that includes a context-calculating unit, parameter-generating unit, arithmetic decoding-calculating unit, stream-converting unit, storage unit, synchronization-detecting unit, and multivalued calculating unit, which together enable parallel processing of bitstreams, synchronizing calculation start timing, and reducing processing loads, thereby facilitating real-time image display.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If arithmetic decoding and context calculation are performed serially as specified in H.264 standard, then decoding accuracy is maintained, but processing speed becomes insufficient for real-time display requiring clock frequencies around 784 MHz which are difficult to design
Solution Approach 1:
The patent divides the decoding process into two distinct stages: an arithmetic decoding stage that processes bitstreams serially to maintain accuracy, and a multivalued calculation stage that processes decoded data in parallel to achieve high speed. This segmentation allows each stage to operate at optimal clock frequencies without requiring the entire system to run at 784 MHz, thereby reducing design difficulty while maintaining real-time display capability.
Solution Approach 2:
The patent introduces an intermediate storage unit that buffers the decoded data between the arithmetic decoding stage and the multivalued calculation stage. This intermediary buffer decouples the timing requirements of the two stages, allowing the arithmetic decoding to proceed at lower clock speeds while the multivalued calculation stage can operate at higher speeds to meet real-time display requirements.
2Productivity
If high clock frequency of 784 MHz is used to meet real-time display requirements, then processing speed is sufficient, but design difficulty and manufacturing complexity increase severely
Solution Approach 1:
The patent segments the decoding functionality into two operational modes: a first mode for arithmetic decoding at lower clock frequencies, and a second mode for multivalued calculation at higher clock frequencies. This allows the apparatus to achieve real-time display productivity without requiring the entire device to be manufactured for high-frequency operation, simplifying manufacturing.
Solution Approach 2:
The patent implements dynamic switching between different processing modes based on the data stage. The arithmetic decoding unit operates at lower frequencies during bitstream processing, while the multivalued calculation unit operates at higher frequencies during image generation. This dynamic operation allows the device to achieve high productivity when needed without requiring permanent high-frequency design, easing manufacturing constraints.
3Measurement precision
If serial processing is used to maintain decoding accuracy, then processing precision is maintained, but processing time increases making real-time display impossible
Solution Approach 1:
The patent segments the processing pipeline into an accuracy-critical serial arithmetic decoding stage and a speed-optimized parallel multivalued calculation stage. The serial processing maintains decoding accuracy for the bitstream interpretation, while the parallel processing accelerates the subsequent multivalued calculations that generate the final image data, thereby reducing overall processing time for real-time display.
Solution Approach 2:
The patent establishes a continuous processing flow where the arithmetic decoding unit continuously processes incoming bitstreams and feeds decoded data to the multivalued calculation unit, which continuously generates image data for display. This continuous operation eliminates idle time and ensures that both accuracy-critical and speed-critical operations proceed without interruption, achieving real-time display performance.
Data Source
AI summary
A decoding-processing apparatus that decodes bitstreams using an intermediate format. The apparatus includes a context-calculating unit (2) calculating the probability of symbols contained in incoming bitstreams, a parameter-generating unit (3) generating parameters for use in the context-calculating unit (2), and an arithmetic decoding-calculating unit (4) decoding the incoming bitstreams in accordance with the probability, thereby providing decoded data. The apparatus also includes a stream-converting unit (5) converting the decoded data into intermediate bitstreams, a storage unit (6) storing the intermediate bitstreams, a synchronization-detecting unit (7) detecting calculation start timing from the intermediate bitstreams fed out of the storage unit (6), thereby providing detected calculation start timing, and a multivalued calculating unit (8) permitting the intermediate bitstreams fed out of the storage unit (6) to be multivalued in synchronism with the detected calculation start timing from the synchronization-detecting unit (7).