Intermediate Buffer Routing for Fragmented Memory Decoding

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Solution Overview

Problem

Conventional information reproducing apparatuses face performance degradation due to excess overhead in data transfer and decoder control when resource data is not arranged in continuous memory areas, leading to inefficient decoding processes.

Innovation Solution

An information reproducing apparatus with a file cache management system that includes an intermediate buffer to ensure data continuity, using a change-over switch to route data through an intermediate buffer for decoding when data is not in continuous areas, and directly to the decoder when it is, optimizing data processing paths based on determination of data arrangement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If data are stored in divided memory areas, then memory management flexibility is improved, but data transfer overhead increases and decoding performance deteriorates

Engineering Contradiction:
Improvememory management flexibilityVSAvoiddecoding performance
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent introduces an intermediate buffer as a mediator between the divided memory areas and the decoder. This intermediate buffer consolidates data from multiple divided memory areas into a continuous data stream, allowing the decoder to process data efficiently without directly accessing fragmented memory regions. The intermediate buffer thus resolves the contradiction by enabling both flexible memory management and efficient decoding performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the memory into multiple divided memory areas for flexible storage management, while simultaneously maintaining a separate intermediate buffer that provides continuous data flow to the decoder. This segmentation allows different parts of the system to operate optimally - the divided memory for flexibility and the continuous buffer for decoding performance.

Inventive Principle:
Principle #1Segmentation

2Productivity

If data are arranged in continuous memory areas, then decoding efficiency is improved, but memory management complexity increases

Engineering Contradiction:
Improvedecoding efficiencyVSAvoidmemory management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The intermediate buffer serves as an intermediary that handles the complexity of managing continuous data streams. It absorbs the memory management complexity by implementing its own buffering and data consolidation logic, while presenting a simple continuous data interface to the decoder. This resolves the contradiction by isolating the complexity in the intermediate buffer rather than in the overall memory management system.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Stability of the object's composition

If an intermediate buffer is introduced, then data continuity for decoding is improved, but system complexity increases

Engineering Contradiction:
Improvedata continuityVSAvoidsystem complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The intermediate buffer is designed as a simple FIFO (first-in, first-out) structure that provides data continuity without complex processing. It simply collects data from divided memory areas and outputs it continuously to the decoder, maintaining data stability and continuity while adding minimal system complexity through its straightforward buffering mechanism.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8060702B2Information reproducing apparatus and information reproducing method
Publication Date: 2011.11.15 MAXELL LTD
  • US8060702B2 patent drawing
  • US8060702B2 patent drawing
  • US8060702B2 patent drawing

AI summary

According to one embodiment, an information reproducing apparatus includes a memory, a decoder, an intermediate memory which is disposed between the memory and the decoder and which temporarily stores, in succession, the data that are supplied from the memory and then outputs the data to the decoder, switching circuit for switching an output of the memory to one of the decoder and the intermediate memory, memory management circuit for managing arrangement information of the data that are stored in the memory, determination circuit for determining whether the data that are stored in the memory are arranged in physically discontinuous memory areas of the memory, and switching control circuit for switching, in a case where the determination circuit determines that the data are arranged in the physically divided memory areas, the switching circuit in a manner to input the data output from the memory to the decoder via the intermediate memory.