Nonvolatile Memory Intermediate Buffers to Prevent Read Thrashing
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Solution Overview
Problem
Existing nonvolatile memory systems face challenges in accelerating processing times for sequential read commands due to thrashing of sense results within the input/output buffer, particularly when multiple threads request data sequentially, leading to repeated sensing operations.
Innovation Solution
Implementing a nonvolatile memory system with multiple intermediate buffers and a control circuit that allocates these buffers to specific threads, allowing for explicit designation and transfer of data to the input/output buffer, thereby reducing unnecessary sensing operations and optimizing data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single input/output buffer is used for sequential read commands from multiple threads, then device complexity is reduced, but processing time increases due to thrashing of sense results and repeated sensing operations
Solution Approach 1:
The patent divides the single input/output buffer into multiple intermediate buffers (first intermediate buffer, second intermediate buffer, etc.), each dedicated to specific threads. This segmentation prevents thrashing by isolating sense results for different threads, eliminating repeated sensing operations and reducing processing time while maintaining manageable device complexity through structured buffer allocation.
Solution Approach 2:
The patent introduces intermediate buffers as intermediary structures between the memory cell array and the input/output buffer. These intermediate buffers serve as mediators that hold sense results for specific threads before transferring to the input/output buffer, preventing direct thrashing between threads and reducing the need for repeated sensing operations.
2Loss of time
If multiple intermediate buffers are allocated to specific threads, then processing time for sequential read commands is reduced by minimizing thrashing, but device complexity increases
Solution Approach 1:
The patent segments the buffer system into multiple intermediate buffers, each associated with specific threads. This segmentation strategy reduces processing time by preventing sense result thrashing between threads while managing device complexity through a systematic allocation approach where each buffer serves a defined thread subset.
Solution Approach 2:
The patent implements a universal buffer management mechanism where intermediate buffers can be dynamically allocated and deallocated based on thread requirements. This multi-functional approach allows the system to adapt to different threading scenarios, reducing processing time when needed while maintaining flexibility to manage complexity in various operational contexts.
3Productivity
If sense results are reused within the input/output buffer, then productivity increases by reducing repeated sensing operations, but reliability decreases due to thrashing and data corruption
Solution Approach 1:
The patent segments the buffer space into thread-specific intermediate buffers, ensuring that sense results for different threads are isolated and reused within their designated buffers. This segmentation prevents cross-thread thrashing and data corruption while maintaining high productivity through efficient sense result reuse, thereby simultaneously improving both productivity and reliability.
Solution Approach 2:
The intermediate buffers act as intermediaries that preserve data integrity by isolating sense results for different threads. This intermediary structure enables reliable data transfer by preventing thrashing while maintaining the ability to reuse sense results efficiently, thus resolving the contradiction between productivity and reliability.
Data Source
AI summary
According to one embodiment, there is provided a nonvolatile memory including a memory cell array, an input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.