Clock Frequency Stepping to Prevent IC Supply Voltage Overshoot
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Solution Overview
Problem
Integrated circuit supply voltage controllers struggle to maintain stable voltage during abrupt changes in load, particularly when modifying clock signal frequencies, leading to overshooting or undershooting, which can exceed operating limits and be dangerous for attached devices.
Innovation Solution
A method involving a series of successive frequency divisions of the clock signal into intermediate frequencies, with varying division ratios, to standardize frequency variations and adapt to the response time of the controller, preventing supply voltage overshoots and undershoots, using a frequency divider with counter-comparators to periodically subtract pulses and manage the clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock signal frequency is modified directly from initial to final frequency, then the frequency modification is simple and fast, but supply voltage overshooting or undershooting occurs which can exceed operating limits
Solution Approach 1:
The frequency modification process is segmented into multiple intermediate steps rather than a single direct transition. The frequency divider is configured to generate intermediate frequencies between the initial and final frequencies, creating a sequence of gradual transitions. This segmentation allows the supply voltage controller to track and stabilize voltage at each intermediate step, preventing overshooting and undershooting while still achieving the frequency modification goal.
2Device complexity
If a conventional frequency divider with division ratio of 1/2 is used, then the frequency division is simple to implement, but for clock frequencies greater than 120 MHz, the amplitude variation remains significant (greater than 60 MHz) causing overshooting or undershooting
Solution Approach 1:
The frequency divider is configured dynamically based on the initial clock frequency. When the initial frequency exceeds 120 MHz, the divider automatically selects an appropriate division ratio from multiple possible ratios (such as 1/4, 1/8, 1/16, or 1/32) rather than being fixed at 1/2. This dynamic configuration ensures that the amplitude variation between intermediate frequencies remains within acceptable limits (less than 60 MHz), preventing supply voltage overshooting and undershooting while maintaining relatively simple circuit implementation.
Data Source
AI summary
A method for modifying the frequency of a clock signal clocking an integrated circuit supplied by a voltage controller, comprises, in response to a command for the modification, varying the frequency of the clock signal at a rate allowing a supply voltage to be controlled by the controller. The variation comprises at least one series of successive divisions of the frequency of the clock signal into successive intermediate signals of respective intermediate frequencies.