Intermediate Die Signal Coupling for Balanced 3D Memory Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As memory speeds increase, the delay between signals arriving at the lowest and highest elevation dies in a 3D memory stack becomes non-negligible, leading to reduced performance due to accommodated timing differences, which traditional methods address by setting operational timing based on the worst case arrival time at the highest die.
Innovation Solution
Providing a signal to an intermediate semiconductor device within a group and propagating it through different signal paths to balance the loading, reducing the timing difference between signal arrivals at each device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If signals are provided to the lowest elevation die and propagated upwards through cascade bonds, then all dies can be connected to external circuits, but the timing difference between signal arrival at lowest and highest dies becomes non-negligible, reducing memory performance
Solution Approach 1:
The patent introduces an intermediate die positioned between the lowest and highest elevation dies to receive and redistribute signals. This intermediary die acts as a signal distribution hub, receiving signals from external circuits and propagating them to multiple dies simultaneously through multiple signal paths, thereby reducing the timing difference between signal arrivals at different dies while maintaining full connectivity.
2Reliability
If operational timing is set based on the worst case signal arrival time at the highest die, then all dies can operate reliably, but memory device performance is reduced due to the accommodated timing differences
Solution Approach 1:
The patent implements dynamic timing adjustment by providing different timing parameters to different dies based on their signal propagation characteristics. Instead of using a single worst-case timing parameter for all dies, the system dynamically adjusts timing parameters individually for each die or group of dies, allowing optimized performance while maintaining reliability through adaptive timing control.
Data Source
AI summary
Apparatuses and methods for coupling semiconductor devices are disclosed. In a group of semiconductor devices (e.g., a stack of semiconductor devices), a signal is provided to a point of coupling at an intermediate semiconductor device of the group, and the signal is propagated away from the point of coupling over different (e.g., opposite) signal paths to other semiconductor devices of the group. Loading from the point of coupling at the intermediate semiconductor device to other semiconductor devices of a group may be more balanced than, for example, having a point of coupling at semiconductor device at an end of the group (e.g., a lowest semiconductor device of a stack, a highest semiconductor device of the stack, etc.) and providing a signal therefrom. The more balanced topology may reduce a timing difference between when signals arrive at each of the semiconductor devices.