Intermediate Language for Heterogeneous Loop Parallelism
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Solution Overview
Problem
Current programming models for heterogeneous devices, such as GPGPU and vector/multi-core architectures, face challenges in efficiently mapping complex iteration spaces and controlling loop parallelism, leading to inefficient memory usage and compilation difficulties, particularly in projecting parallelism across different hardware configurations.
Innovation Solution
A method and system for generating an intermediate language version of computer program code that includes information about parallelism, allowing for runtime optimization based on device characteristics, enabling thread or vector parallelism, and separating the intermediate language version from the source code for improved control and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If current GPGPU programming models are used to map complex iteration spaces, then code can be executed on graphics hardware, but information is lost and remapping becomes difficult
Solution Approach 1:
The patent segments the iteration space mapping into multiple levels: a high-level iteration space description that preserves semantic information, and a lower-level work item grouping that maps to hardware. This segmentation allows the high-level description to retain information while the low-level mapping optimizes for hardware execution.
Solution Approach 2:
The patent introduces an intermediate representation layer between the high-level iteration space and the hardware work items. This intermediary preserves the original iteration space semantics while enabling flexible mapping to different hardware configurations, preventing information loss during the mapping process.
2Ease of operation
If work items are grouped into static groups, then synchronization and memory structures can be defined, but the mapping becomes inflexible for different hardware
Solution Approach 1:
The patent makes the work item grouping dynamic rather than static. The system can adjust the number and size of work item groups based on the target hardware configuration, allowing the same high-level code to adapt to different GPU architectures without requiring manual remapping of the iteration space.
Solution Approach 2:
The patent adds an additional dimension of abstraction between the iteration space and hardware mapping. This extra layer allows memory structures to be defined in terms of the iteration space semantics rather than fixed work group boundaries, providing both ease of operation and hardware adaptability.
3Ease of manufacture
If compiler-driven parallelism inference is used, then standard C code can be parallelized, but the compiler may fail to vectorize code in the desired way
Solution Approach 1:
The patent performs preliminary parallelism specification in the high-level iteration space description, where the programmer explicitly indicates parallelism opportunities before compilation. This preliminary action guides the compiler's vectorization and parallelization decisions, ensuring that the desired parallelism is achieved without relying solely on compiler inference.
Data Source
AI summary
A method, a system, and a non-transitory computer readable medium for parallelizing computer program code including a loop are presented. An intermediate language version of the computer program code is generated based on a parallel type of the loop, wherein the intermediate language version includes information about parallelism in the computer program code. The intermediate language version is optimized at runtime based on the device characteristics where the computer program code is to be executed. The parallel type may include a thread parallel type, wherein the loop is dispatched to multiple threads for execution, or a general parallel type, wherein the loop is dispatched to a single thread and may be vectorized for execution. The intermediate language version may be saved separate from the computer program code.