Intermediate Processor Memory Mapping for Instruction–Data Separation
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Solution Overview
Problem
Existing microprocessors face inefficiencies and performance bottlenecks due to dual use of RAM for storing both data and instructions, leading to unwanted competition for memory resources and inefficient consumption of capacity.
Innovation Solution
Implementing separate memory subsystems for instruction and data storage, with dedicated ports and channels, and using a RAM block allocator to configure memory blocks at deployment time for optimal allocation based on configuration signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If RAM is used for storing both data and instructions, then memory capacity is reduced, but performance bottlenecks and resource competition occur
Solution Approach 1:
The patent divides the memory system into separate instruction memory and data memory subsystems. The microprocessor has dedicated instruction ports and data ports that access separate RAM blocks, eliminating resource competition between instruction fetch and data access operations. This segmentation resolves the contradiction by providing sufficient dedicated memory capacity for both functions while eliminating performance bottlenecks caused by shared memory access.
2Productivity
If separate memory subsystems are implemented, then performance is improved, but device complexity increases
Solution Approach 1:
The patent implements a microprocessor with multi-functional capabilities where the same processor can operate with different memory configurations. The processor includes both instruction ports and data ports that can be configured to access different RAM blocks based on the specific application requirements. This universality allows the system to achieve high performance through separate memory subsystems while maintaining flexibility to adapt to different complexity requirements.
3Device complexity
If fixed memory allocation is used, then device complexity is reduced, but adaptability to different configurations is limited
Solution Approach 1:
The patent implements dynamic memory allocation capabilities where the memory configuration can be changed based on operational requirements. The microprocessor includes configuration mechanisms that allow the instruction ports and data ports to be dynamically assigned to different RAM blocks. This dynamic allocation provides adaptability to different memory configurations while maintaining relatively simple device architecture through standardized configuration interfaces.
Data Source
AI summary
A system includes first memory, a controller, and a processor. The controller is indirectly connected to the memory, configured to perform at least one function, and configured to handle data generated or received during performance of the at least one function. The processor is connected between the memory and the controller. The processor reconfigures a map before and during performance of the at least one function by the controller. The reconfiguring of the map includes changing i) a first allocated portion of the memory for program instructions, and ii) a second allocated portion of the memory for the data. The processor, based on the map, i) routes the program instructions and the data between the controller and the first memory, ii) stores the program instructions at addresses of the memory allocated for the program instructions, and iii) stores the data at addresses of the memory allocated for the data.