Intermediate Metal Routing Layer for Display Circuitry
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Solution Overview
Problem
Mobile electronic devices with touch screens face a challenge in maximizing display area due to the presence of inactive border areas required for signal routing, which limits the available space for display and touch interaction.
Innovation Solution
The solution involves forming additional metal routing structures between conventional M1 and M2 metal routing layers with lower resistance, allowing for thinner routing paths and interlaced signal routing, which reduces the inactive border area and increases the active display region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional metal routing layers (M1, M2) are used for signal routing, then routing paths can be formed, but the routing resistance is high requiring wider routing paths and larger inactive border area
Solution Approach 1:
The patent introduces an intermediate routing layer positioned between the conventional M1 and M2 metal layers, transitioning from a two-layer routing structure to a three-layer structure. This dimensional addition in the vertical stack enables lower resistance routing paths without increasing the lateral border area, directly resolving the contradiction between routing reliability and active display area.
Solution Approach 2:
The patent employs composite material structures in the routing layers, using different metal compositions and thicknesses optimized for electrical conductivity. The intermediate layer uses materials specifically selected to provide lower resistance compared to conventional layers, enabling efficient signal routing with reduced width requirements and thus maximizing the active display region.
2Reliability
If wider routing paths are used to reduce routing resistance, then routing reliability improves, but the inactive border area increases reducing the display area
Solution Approach 1:
By adding the intermediate routing layer in the vertical dimension, the patent distributes routing functions across multiple layers. This allows each individual layer to use narrower, more efficient path widths while collectively providing robust, low-resistance routing, thereby reducing the inactive border area and maximizing the active display region without compromising routing reliability.
Solution Approach 2:
The routing function is segmented across three separate layers instead of relying on fewer wider paths. Each layer handles specific routing tasks with optimized width and material properties, distributing the electrical load and reducing the resistance without requiring any single layer to occupy excessive lateral space, thus preserving maximum active display area.
3Area of moving object
If the inactive border area is reduced to maximize display area, then the active display region increases, but routing space becomes insufficient
Solution Approach 1:
The patent resolves the space constraint by utilizing the vertical dimension with an intermediate routing layer positioned between M1 and M2. This three-layer vertical architecture provides sufficient routing capacity within a compact lateral footprint, enabling reduced inactive border area while maintaining complete routing functionality without excessive complexity.
Solution Approach 2:
The intermediate routing layer serves multiple functions: providing low-resistance signal paths, enabling interlaced signal routing patterns, and facilitating compact routing density. This multi-functional design allows the routing structure to achieve high efficiency within minimal border space, maximizing the active display region without proportionally increasing device complexity.
Data Source
AI summary
A display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (TFT) layer. The TFT layer may include thin-film transistors formed on top of a glass substrate. A passivation layer may be formed on the thin-film transistor layers. An oxide liner may be formed on the passivation layer. A first low-k dielectric layer may be formed on the oxide liner. A second low-k dielectric layer may be formed on the first low-k dielectric layer. A common voltage electrode and associated storage capacitance may be formed on the second low-k dielectric layer. Thin-film transistor gate structures may be formed in the passivation layer. Conductive routing structures may be formed on the oxide liner, on the first low-k dielectric layer, and on the second low-k dielectric layer. The use of routing structures on the oxide liner reduces overall routing resistance and enables interlaced metal routing, which can help reduce the inactive border area outside the active display regions.