Intermediate Residual Test Modes for SoC DFT
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Solution Overview
Problem
Existing Design-for-Test (DFT) techniques for Systems-on-Chips (SoCs) face challenges in reducing test time and power consumption, particularly for unwrapped cores, where traditional full residual test modes are expensive and offer limited compression, leading to increased test time and power dissipation.
Innovation Solution
The implementation of intermediate residual test modes that do not span all cores or flip-flops, using a reconfigurable scan segment architecture and scan router logic to group flip-flops into test groups and modes based on core interactions, allowing for partial residual test modes that integrate with on-chip test compression solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full residual test mode is used to test all cores and flip-flops in an SoC, then complete coverage of top-level logic and inter-core interactions is achieved, but test time and power consumption increase significantly
Solution Approach 1:
The patent segments the scan chains into core-internal scan chains and residual scan chains. Core-internal scan chains test individual cores, while residual scan chains test only the top-level logic and inter-core interactions. This segmentation allows selective testing rather than requiring all flip-flops to participate in full residual test mode, thereby reducing test time while maintaining coverage of critical top-level logic.
Solution Approach 2:
The patent implements partial residual test mode where only a subset of scan chains (those necessary for top-level logic coverage) are reconfigured into residual scan chains, rather than requiring all scan chains to participate. This partial action approach achieves sufficient test coverage for top-level logic without the excessive test time and power consumption of full residual test mode.
2Reliability
If full residual test mode is used to test all cores and flip-flops in an SoC, then complete coverage of top-level logic and inter-core interactions is achieved, but power dissipation increases substantially
Solution Approach 1:
The patent segments the scan chains into core-internal scan chains and residual scan chains. By segmenting the test infrastructure, only the necessary residual scan chains are activated during top-level testing, reducing the number of active flip-flops and thereby reducing power dissipation compared to full residual test mode where all flip-flops would be active.
Solution Approach 2:
The patent applies different test modes to different parts of the design: core-internal test mode for individual cores and partial residual test mode for top-level logic. This local quality approach ensures that power-intensive residual test mode is applied only where necessary (top-level logic coverage) rather than uniformly across the entire SoC, reducing overall power dissipation.
3Loss of time
If hierarchical scan testing is implemented with core-internal test modes, then test time for individual cores is reduced, but top-level logic testing becomes more complex due to reconfiguration requirements
Solution Approach 1:
The patent segments scan chains into distinct core-internal scan chains and residual scan chains with different reconfiguration behaviors. Core-internal scan chains remain relatively simple and are not reconfigured during top-level testing, while residual scan chains are specifically designed for top-level logic coverage. This segmentation simplifies the overall reconfiguration complexity compared to a fully reconfigurable hierarchical system.
Data Source
AI summary
A technique for reducing the overhead of daisy chain test mode in divide-and-conquer testing using intermediate test modes that do not span all cores or all flip-flops in the core. The partial residual test mode spans across a subset of the cores and allows to bound the number of cores that a full residual test mode may span across. The interaction of the cores among one another at the top-level is analyzed and the minimum number of flip-flops in a core that must participate in a intermediate test mode is selected. Algorithms are devised to analyze the interactions among the cores and build data structures which are used for identifying intermediate test modes. Using a reconfigurable scan segment architecture, intermediate test modes are implemented that are designed to work with all known test compression solutions. Since the length of the longest scan chain in an intermediate residual test mode is much smaller than the length of the longest scan chain in the full residual test mode, there is a substantial improvement in test application time as well as test peak power.