Intermediate Rounding in Fused Multiply-Add Instructions

Solution Overview

Problem

Existing floating-point operations in computing systems face challenges due to limited precision, leading to inconsistent rounding in fused multiply-add and multiply-subtract instructions, which can result in bitwise reproducibility issues.

Innovation Solution

Implementing instructions that perform intermediate rounding for both multiplication and addition/subtraction results, allowing for two rounds of rounding, which aligns with software expectations and improves reproducibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If only final rounding is performed after addition/subtraction in fused multiply-add instructions, then device complexity is reduced, but measurement precision and reproducibility deteriorate due to inconsistent rounding results

Engineering Contradiction:

Improverounding operation countVSAvoidfloating-point calculation precision

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The patent applies preliminary rounding to the multiplication result before performing the addition/subtraction operation. This intermediate rounding step ensures that the multiplication result is rounded to the target precision before being used in subsequent operations, which guarantees bitwise reproducibility across different hardware implementations while maintaining reasonable device complexity.

Inventive Principle:

Principle #10Preliminary action

2Measurement precision

If intermediate rounding is performed after multiplication in fused multiply-add instructions, then measurement precision and reproducibility are improved, but device complexity increases due to additional rounding operations

Engineering Contradiction:

Improvefloating-point calculation precisionVSAvoidrounding operation count

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary rounding to the multiplication result before performing the addition/subtraction operation. This intermediate rounding step ensures that the multiplication result is rounded to the target precision before being used in subsequent operations, which guarantees bitwise reproducibility across different hardware implementations while maintaining reasonable device complexity.

Inventive Principle:

Principle #10Preliminary action

3Ease of operation

If no intermediate rounding is performed in fused multiply-add instructions, then ease of operation is maintained with simple single rounding, but reliability deteriorates due to bitwise non-reproducibility across different systems

Engineering Contradiction:

Improveoperation simplicityVSAvoidbitwise reproducibility

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The patent applies preliminary rounding to the multiplication result before performing the addition/subtraction operation. This intermediate rounding step ensures that the multiplication result is rounded to the target precision before being used in subsequent operations, which guarantees bitwise reproducibility across different hardware implementations while maintaining reasonable device complexity.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20240103865A1Vector multiply-add/subtract with intermediate rounding

Publication Date: 2024.03.28 INTEL CORP

AI summary

Techniques for using and/or supporting multiplication with add and/or subtract instructions with an intermediate (after multiplication) round are described. In some examples, an instruction at least having one or more fields for an opcode and location information for three packed data source operands, wherein the opcode is to indicate execution circuitry is to perform, per packed data element position, a multiplication, a round, addition and/or subtraction, and a round, using the three packed data source operands and storage into a corresponding packed data element position of an identified destination location, wherein which packed data element positions are to be added and subtracted is defined by the opcode is supported.