Intermediate Routing Layers for Dense 3D IC Die Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor packaging technologies face challenges with low vertical and horizontal interconnect density, leading to routing congestion, signal loss, and reduced die placement flexibility in multi-layer IC die stacks, particularly in complex server architectures.
Innovation Solution
A microelectronic assembly with a quasi-monolithic hierarchical integration architecture using silicon-level interconnect density, comprising multiple IC dies stacked with conductive routing traces in a dielectric layer, and die-to-die interconnects with sub-10 micrometer pitch, enabling efficient lateral and vertical electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional packaging technologies are used, then manufacturing simplicity is maintained, but interconnect density is low leading to routing congestion
Solution Approach 1:
The patent transitions from planar 2D routing to 3D vertical stacking with multiple layers, enabling signals to route through the vertical dimension. This dimensional change allows multiple interconnect paths without increasing lateral routing congestion, achieving high interconnect density while maintaining manageable complexity through systematic layer design.
Solution Approach 2:
The packaging architecture is segmented into multiple discrete layers with dedicated routing functions. Each layer handles specific signal types or routing domains, allowing independent optimization of each layer's interconnect density without creating system-wide routing conflicts, thus resolving the contradiction between density and complexity.
2Reliability
If interconnect density is increased to reduce routing congestion, then signal integrity improves, but manufacturing complexity increases
Solution Approach 1:
Different layers are assigned different routing qualities and functions based on local requirements. High-speed signals use dedicated layers with optimized impedance control, while lower-priority signals use shared layers. This local differentiation achieves high signal integrity for critical paths without requiring maximum complexity across the entire routing architecture.
3Quantity of substance
If multi-layer stacking is implemented to improve interconnect density, then routing congestion is reduced, but die placement flexibility is reduced
Solution Approach 1:
The intermediate layers serve multiple functions simultaneously: they provide vertical interconnect routing, enable die placement flexibility through standardized interfaces, and offer thermal management pathways. This multi-functionality allows the same architectural structure to achieve high vertical interconnect density while maintaining adaptability for different die placement configurations.
Data Source
AI summary
Embodiments of the present disclosure provide a microelectronic assembly comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer; and a third layer between the first layer and the second layer, the third layer comprising conductive routing traces in a dielectric. A first interface is between the first layer and the third layer and includes first interconnects having a first pitch of less than 10 micrometers between adjacent ones of the first interconnects, a second interface is between the second layer and the third layer and includes second interconnects having a second pitch of less than 10 micrometers between adjacent ones of the second interconnects, and the routing traces in the third layer are to provide lateral electrical coupling between the first interconnects and the second interconnects.