Intermediate Semiconductor Layer Potential Fixing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices with stacked semiconductor layers and insulator films, positive charges at the periphery of the intermediate semiconductor layer can lead to inversion layers, causing the layer to become electrically floating and potentially erroneous operation of transistors due to capacitive coupling with the high-voltage semiconductor layer.
Innovation Solution
A semiconductor device configuration where the intermediate semiconductor layer, either n-type or p-type, is designed with a specific thickness and contact regions to prevent contiguous inversion layers, ensuring the layer can be fixed to a desired potential by applying ground potential through a contact electrode, thereby suppressing the influence of high voltage on circuit elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the intermediate semiconductor layer is fixed to ground potential to prevent high voltage from reaching the first semiconductor layer, then the second semiconductor layer can be depleted with high voltage, but positive charges charged during plasma manufacturing processes cause inversion layers to form inside the third semiconductor layer, making it electrically floating and unable to maintain the desired potential
Solution Approach 1:
A charge neutralization layer is introduced as an intermediary between the first and third semiconductor layers. This layer absorbs positive charges generated during plasma manufacturing processes, preventing them from creating inversion layers in the third semiconductor layer. The charge neutralization layer acts as a mediator that protects the third layer's electrical potential stability while allowing the second layer to function with high voltage depletion.
Solution Approach 2:
The charge neutralization layer is formed in advance during the manufacturing process, before the plasma etching or CVD steps that generate positive charges. By pre-positioning this charge-absorbing layer, the system proactively prevents inversion layer formation rather than attempting to correct it afterward, ensuring the third semiconductor layer maintains its grounded potential throughout subsequent manufacturing steps.
2Ease of manufacture
If the third semiconductor layer is made thinner to reduce inversion layer impact, then the manufacturing process becomes easier, but the layer may not be sufficient to block capacitive coupling between high voltage and the first semiconductor layer
Solution Approach 1:
The charge neutralization layer serves as a mediator that compensates for reduced thickness of the third semiconductor layer. Even when the third layer is made thinner for ease of manufacture, the charge neutralization layer absorbs positive charges that would otherwise create inversion layers, maintaining voltage isolation effectiveness through charge management rather than relying solely on physical thickness.
3Reliability
If the third semiconductor layer is made thicker to improve voltage isolation, then capacitive coupling is reduced, but the manufacturing precision required to control the layer thickness increases
Solution Approach 1:
The charge neutralization layer is formed preliminarily during the manufacturing sequence, allowing the third semiconductor layer thickness to be optimized for voltage isolation without excessive precision requirements. The pre-formed charge neutralization layer provides a safety margin that compensates for normal manufacturing variations in the third layer thickness, reducing the need for ultra-precise thickness control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reliably fixes the intermediate semiconductor layer to a desired potential, preventing erroneous operation of transistors and ensuring accurate voltage application, even in the presence of positive charges, by maintaining non-contiguous inversion layers and ensuring the layer remains grounded.
Implementation Method 1
a contact electrode connected to the intermediate semiconductor layer... applying ground potential through a contact electrode, thereby suppressing the influence of high voltage on circuit elements
Implementation Method 2
positive charges charged in the vicinity of a boundary between the third semiconductor layer and the first insulator layer, and charged in the vicinity of a boundary between the third semiconductor layer and the second insulator layer, retain. Inversion layers are thereby formed inside the third semiconductor layer
Implementation Method 3
a first insulator layer provided above the first semiconductor layer... a second insulator layer provided above the intermediate semiconductor layer
Data Source
AI summary
A semiconductor device including a first semiconductor layer including a first region and a second region adjacent to the first region; a first insulator layer provided above the first semiconductor layer; an intermediate semiconductor layer, having an n-type conduction, provided above the first region of the first semiconductor layer and above the first insulator layer; a second insulator layer provided above the intermediate semiconductor layer; a second semiconductor layer provided above the first region of the first semiconductor layer and above the second insulator layer; a sensor formed in the second region of the first semiconductor layer; a contact electrode connected to the intermediate semiconductor layer; and a circuit element formed in the second semiconductor layer.