Intermediate Value Scaling for Low-Precision Floating-Point Arithmetic
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Solution Overview
Problem
Arithmetic operations using floating-point numbers represented by fewer than 16 bits face increased likelihood of overflow and underflow due to reduced representable value range, which can be exacerbated by misalignment between input value distribution and FP format representation, and converting to higher precision formats may negate performance gains.
Innovation Solution
A processing device with a control register for scaling factors applies these factors to result values in a format with more bits, allowing a greater range of representation, thereby preventing overflow or underflow without converting input values to higher precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If floating-point numbers with fewer than 16 bits are used, then storage space and circuitry requirements are reduced, but the range of representable values decreases, increasing overflow and underflow likelihood
Solution Approach 1:
The patent introduces an intermediary format (mixed precision format) that combines a smaller exponent field with a larger mantissa field to represent intermediate calculation results. This intermediary representation allows the system to maintain lower precision for storage efficiency while providing sufficient range for intermediate values, thereby preventing overflow and underflow without requiring full-precision formats throughout the computation.
Solution Approach 2:
The patent dynamically changes the parameters of the floating-point representation by adjusting the allocation between exponent and mantissa bits based on the calculation stage. For intermediate results, it uses a format with more mantissa bits and fewer exponent bits, while for final results it transitions to the standard format. This parameter adaptation allows the system to optimize both range and precision as needed.
2Reliability
If input values are converted to higher precision formats, then overflow and underflow are prevented, but performance gains from lower precision are negated
Solution Approach 1:
The patent applies different precision formats to different parts of the computation process. Instead of converting all values to high precision, it selectively uses the extended mixed precision format only for intermediate results where additional range is needed, while maintaining low precision for input values and final outputs. This localized application of higher precision prevents overflow/underflow in critical areas without sacrificing overall performance.
Solution Approach 2:
The patent segments the floating-point number representation into distinct components with different bit allocations for intermediate results. By dividing the representation into a smaller exponent field and larger mantissa field, it creates a specialized format that provides the necessary range for intermediate calculations while maintaining efficiency. This segmentation allows the system to handle intermediate values differently from input and output values.
3Productivity
If lower precision floating-point formats are used, then more operations can be performed in parallel, but the distribution of input values may not align with the representable value range
Solution Approach 1:
The patent introduces dynamic format conversion that adapts the precision format based on the characteristics of the input data and the stage of computation. The system can dynamically switch between standard low-precision format and the extended mixed-precision format for intermediate results, allowing it to accommodate different input value distributions while maintaining high operational throughput. This dynamic adaptation enables the system to handle diverse workloads efficiently.
Data Source
AI summary
A processing device comprising: a control register configured to store a scaling factor; at least one execution unit configured to execute instructions to perform arithmetic operations on input floating-point numbers provided according to a first floating-point format, wherein each of the input floating-point numbers provided according to the first floating-point format comprises a predetermined number of bits, wherein the at least one execution unit is configured to, in response to execution of an instance of a first of the instructions: perform processing of a first set of the input floating-point numbers to generate a result value, the result value provided in a further format and comprising more the predetermined number of bits, enabling representation of a greater range of values than is representable in the first floating-point format; and apply the scaling factor specified in the control register to increase or decrease an exponent of the result value.