Intermediate-Voltage Level Shifter for Stable High-Speed Conversion

Solution Overview

Problem

Conventional level conversion circuits face instability and high parasitic capacitance issues due to large voltage differences, leading to insufficient signal inversion and increased current consumption, especially at high frequencies.

Innovation Solution

A level conversion circuit with an intermediate voltage generating portion and buffer portions operating between a first and second power supply voltage, allowing for a smaller amplitude ratio between input and output signals, thereby stabilizing the circuit and reducing parasitic capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the gate width of N channel MOS transistors is increased to improve driving capability, then the driving capability is improved, but parasitic capacitance increases and high speed operation is not achieved

Engineering Contradiction:

Improvedriving capabilityVSAvoidoperation speed

Core Design Contradiction:

PowerVSSpeed

Solution Approach 1:

The patent divides the level conversion circuit into multiple stages: a first level conversion circuit and a second level conversion circuit. The first circuit handles the initial voltage level conversion while the second circuit completes the conversion to the final voltage level. This segmentation allows each stage to operate with optimized transistor dimensions, avoiding the need for excessively large gate widths in a single stage while maintaining sufficient driving capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediate voltage level between the input and output voltage levels. The first level conversion circuit converts the input signal to this intermediate level, and the second level conversion circuit converts it to the final output level. This intermediary approach distributes the voltage conversion task across multiple circuits, reducing the parasitic capacitance burden on individual transistors while maintaining overall driving capability.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Power

If the gate width of N channel MOS transistors is increased to improve driving capability, then the driving capability is improved, but circuit area increases

Engineering Contradiction:

Improvedriving capabilityVSAvoidcircuit area

Core Design Contradiction:

PowerVSArea of stationary object

Solution Approach 1:

The patent divides the level conversion circuit into multiple stages: a first level conversion circuit and a second level conversion circuit. The first circuit handles the initial voltage level conversion while the second circuit completes the conversion to the final voltage level. This segmentation allows each stage to operate with optimized transistor dimensions, avoiding the need for excessively large gate widths in a single stage while maintaining sufficient driving capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediate voltage level between the input and output voltage levels. The first level conversion circuit converts the input signal to this intermediate level, and the second level conversion circuit converts it to the final output level. This intermediary approach distributes the voltage conversion task across multiple circuits, reducing the parasitic capacitance burden on individual transistors while maintaining overall driving capability.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Device complexity

If a conventional level conversion circuit is used with large voltage difference, then the circuit structure is simple, but the operation becomes unstable and signal inversion is insufficient

Engineering Contradiction:

Improvecircuit structureVSAvoidoperation stability

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent divides the level conversion circuit into multiple stages: a first level conversion circuit and a second level conversion circuit. The first circuit handles the initial voltage level conversion while the second circuit completes the conversion to the final voltage level. This segmentation allows each stage to operate with optimized transistor dimensions, avoiding the need for excessively large gate widths in a single stage while maintaining sufficient driving capability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediate voltage level between the input and output voltage levels. The first level conversion circuit converts the input signal to this intermediate level, and the second level conversion circuit converts it to the final output level. This intermediary approach distributes the voltage conversion task across multiple circuits, reducing the parasitic capacitance burden on individual transistors while maintaining overall driving capability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS7999574B2Level conversion circuit and solid-state imaging device using the same

Publication Date: 2011.08.16 KK TOSHIBA

AI summary

According to one embodiment, a level conversion circuit includes an intermediate voltage generating portion to generate an intermediate voltage between a first voltage and a second voltage upon receiving the first voltage and the second voltage higher than the first voltage. A buffer portion operates on the intermediate voltage upon receiving a first signal and an inverted first signal of a first amplitude corresponding to the first voltage. The buffer portion outputs a second signal and an inverted second signal having a second amplitude corresponding to the intermediate voltage. A level shift portion operates on the second voltage upon receiving the second signal and the inverted second signal, and outputs a third signal and an inverted third signal having a third amplitude corresponding to the second voltage.