Intermediation Processor Shared Memory Network Latency

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Solution Overview

Problem

Existing computing systems face challenges in minimizing latency when processing and transmitting messages over networks, particularly in applications like remote game processing where low latency is crucial for user experience.

Innovation Solution

A system comprising a message processor and an intermediation processor that utilizes a shared memory within the address space of the message processor, allowing for efficient message processing and transmission over a physical channel, with the intermediation processor dispatching messages over the network and providing received messages to the message processor, thereby reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If a message processor directly interfaces with the network, then network communication is simple, but latency increases

Engineering Contradiction:
Improvemessage processing latencyVSAvoidprocessor architecture complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

An intermediation processor is introduced between the message processor and the network. The message processor writes messages to a shared memory portion within its address space, and the intermediation processor reads from this shared memory and dispatches messages over the network. This intermediary architecture reduces latency by allowing the message processor to operate independently without waiting for network operations, while the intermediation processor handles all network communication.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If memory is shared between processors, then communication efficiency improves, but address space management becomes complex

Engineering Contradiction:
Improvemessage processing throughputVSAvoidaddress space management
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The shared memory portion is placed within the address space of the message processor, allowing the message processor to directly write messages to shared memory without complex address translation. The intermediation processor acts as the mediator that reads from this shared memory and handles network communication, simplifying address space management while maintaining high communication efficiency.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9467526B2Network communication using intermediation processor
Publication Date: 2016.10.11 MICROSOFT TECHNOLOGY LICENSING LLC
  • US9467526B2 patent drawing
  • US9467526B2 patent drawing
  • US9467526B2 patent drawing

AI summary

Cooperative interaction of a message processor and an intermediation processor. The message processor processes messages received from a network and to be sent over a network. The intermediation processor intermediates between the message processor and the network using a shared memory that includes a memory portion that is within the address space of the message processor. The message processor writes messages into the memory portion over a physical channel and reads message from the memory portion over the physical channel. The intermediation processor provides messages received from a network into the memory portion so that the received messages can be read by the message processor over the physical channel. The intermediation processor dispatches messages written to the memory portion by the message processor over the network.