Intermetal Connections for Vertically Stacked Transistor Contacts
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area through reduced minimum feature sizes, challenges arise in reducing contact resistance and thermal budget concerns in stacked transistors, which affect device performance and manufacturing ease.
Innovation Solution
The formation of complementary field effect transistors (CFETs) with vertically stacked n-type and p-type transistors, where gate and source/drain contacts are directly connected through an intermetal structure, using low resistance materials like tungsten or cobalt, and process steps are delayed to form high-k gate dielectrics after forming semiconductor layers to reduce damage risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but contact resistance increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar transistor stacking to vertically stacked three-dimensional transistor structures. By moving to a vertical dimension, the design achieves higher integration density while maintaining controlled contact resistance through dedicated contact holes and interlayer dielectric structures that bridge the gap between stacked transistors.
Solution Approach 2:
The patent introduces intermediate contact structures including contact holes filled with conductive materials and interlayer dielectric layers that serve as mediators between stacked transistors. These intermediary structures enable electrical connection while managing the increased complexity and resistance issues arising from three-dimensional integration.
2Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but manufacturing complexity increases
Solution Approach 1:
The patent segments the manufacturing process into distinct stages: forming lower transistors, depositing interlayer dielectric, forming contact holes, filling conductive materials, and forming upper transistors. This segmentation allows each step to be optimized independently, managing overall manufacturing complexity while achieving high integration density through vertical stacking.
Solution Approach 2:
The patent performs preliminary actions by forming the lower transistor structure, interlayer dielectric, and contact holes before depositing the upper transistor layer. This preliminary preparation simplifies subsequent processing steps and enables precise alignment, reducing manufacturing complexity despite the three-dimensional architecture.
3Temperature
If process steps are delayed to form high-k gate dielectrics after forming semiconductor layers, then thermal budget concerns are reduced, but process sequence complexity increases
Solution Approach 1:
The patent forms semiconductor layers and contact structures before forming the high-k gate dielectric layer. This preliminary action sequence allows subsequent thermal processing to be performed at lower temperatures that do not damage previously formed structures, effectively managing thermal budget constraints while maintaining process sequence organization.
Solution Approach 2:
The patent dynamically adjusts the process sequence based on thermal sensitivity. By forming temperature-sensitive structures like high-k gate dielectrics after robust semiconductor layers and contact structures are in place, the process adapts thermal constraints to protect delicate materials while maintaining manufacturing feasibility.
Data Source
AI summary
A device includes a first transistor layer comprising a first gate electrode and a second transistor layer comprising a second gate electrode that is stacked with the first transistor layer. An intermetal structure comprising a conductive line is disposed between the first transistor layer and the second transistor layer. A first gate contact extends along a sidewall of the first gate electrode from a top surface of the first gate electrode to the conductive line 48G. A second gate contact extends along a sidewall of the second gate electrode from a top surface of the second gate electrode to the conductive line. The first gate electrode is electrically connected to the second gate electrode by the first gate contact, the second gate contact, and the conductive line.