Print Component Memory Arrays Using Intermittent Clock Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing print components with data parser circuitry consume large silicon area, increase die size and cost, and introduce electromagnetic interference (EMI) issues, while being inflexible and requiring fixed-length fire pulse group data packets.
Innovation Solution
Implementing an array of memory elements in print components to serially receive data segments using an intermittent clock signal, eliminating data parser circuitry and allowing for arrays of fluid actuators with varying primitive sizes to share a clock and fire signals, reducing interconnect complexity and EMI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data parser circuitry is implemented in print components, then data segments can be processed, but silicon area increases and die size and cost increase
Solution Approach 1:
The patent extracts the data parsing function from dedicated circuitry and implements it using memory elements (flip-flops) that already exist in the print component. By reusing the memory array and clock signal infrastructure, the design eliminates separate parser circuitry while maintaining data segmentation and processing capabilities, thereby reducing silicon area.
Solution Approach 2:
The memory elements serve dual purposes: they function as both data storage registers and as data parsing structures. The same memory array and clock signal that control fluid actuator timing also handle data segment reception and parsing, allowing one component to perform multiple functions and reducing overall circuit complexity and area.
2Adaptability or versatility
If data parser circuitry is implemented in print components, then data segments can be processed, but electromagnetic interference is introduced
Solution Approach 1:
The patent removes the data parser circuitry that generates electromagnetic interference and replaces it with a memory-based approach. By using memory elements and a shared clock signal instead of dedicated parser logic, the design eliminates the source of EMI while preserving the ability to process data segments.
3Device complexity
If fixed-length fire pulse group data packets are required, then data parsing can be simplified, but flexibility is reduced
Solution Approach 1:
The patent implements a dynamic data packet structure where the length of fire pulse group data packets can vary. The memory elements and clock signal system accommodate packets of different lengths by dynamically loading the appropriate number of data segments, allowing the system to adapt to different printing requirements without being constrained to fixed-length packets.
4Adaptability or versatility
If arrays of fluid actuators with varying primitive sizes are used, then printing flexibility is improved, but interconnect complexity increases
Solution Approach 1:
The patent uses a universal clock signal and memory element structure that works with fluid actuator arrays of varying sizes. The same clock signal infrastructure and memory array that control small actuator arrays can also control larger arrays, eliminating the need for separate interconnect structures for each array size and reducing overall system complexity.
Data Source
AI summary
A print component includes a plurality of data pads, a clock pad to receive an intermittent clock signal, and a plurality of actuator groups each corresponding to a different liquid type and to a different one of the data pads. Each actuator group includes a plurality of configuration functions, an array of fluid actuators, and an array of memory elements including a first portion corresponding to the plurality of configuration functions and a second portion corresponding to the array of fluid actuators. Each time the intermittent clock signal is present on the clock pad, the array of memory elements to serially load a segment of data bits from the corresponding data pad, including loading a first portion of data bits into the first portion of memory elements, and loading a second portion of data bits into the second portion of memory elements.