Intermittent Clock Generator for Peak Current Smoothing
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Solution Overview
Problem
Existing clock generators for synchronous logic circuits face issues with peak power fluctuations due to irregular switching timing of transistors and lack of oscillation timing adjustment, especially during parallel processing, leading to increased power consumption.
Innovation Solution
A clock generator system that includes a counter and storage units to generate intermittent clock signals based on a reference clock, with bitmap information controlling the oscillation timing to scatter peak power generation across logic circuits, minimizing total current fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operating clock is generated intermittently with continuous and idle periods occurring consecutively, then the processing speed can be adjusted, but the peak current increases
Solution Approach 1:
The patent applies periodic action by generating intermittent clock signals with continuous periods and idle periods repeated at specific ratios (e.g., 3:1 for 75% processing speed). This allows the clock to be suspended during idle periods to reduce power consumption while maintaining operation during continuous periods for required processing, thereby adjusting productivity while managing peak current through controlled periodic interruption.
Solution Approach 2:
The patent applies dynamics by making the clock signal characteristics variable rather than fixed. The clock rate control circuit dynamically adjusts the clock waveform based on processing speed requirements, changing the ratio of continuous to idle periods. This dynamic adjustment allows the system to optimize between processing speed and peak current consumption according to actual workload demands.
2Use of energy by moving object
If the operating clock is generated intermittently to reduce power consumption, then energy usage decreases, but the timing of peak power coincides across multiple logic circuits increasing total peak power
Solution Approach 1:
The patent applies asymmetry by introducing phase shifts to different clock signals supplied to multiple logic circuits. Instead of all circuits receiving intermittent clocks with identical timing, each circuit receives a clock with a different phase offset. This asymmetric timing distribution scatters the peak power occurrences across different time points, preventing simultaneous peak power coincidence while maintaining individual circuit power savings.
Solution Approach 2:
The patent applies preliminary action by pre-adjusting the phase of clock signals before they are supplied to different logic circuits. The clock rate control circuit proactively introduces phase shifts to future clock waveforms, ensuring that when multiple circuits operate in parallel, their peak power consumption occurs at different times. This preliminary phase adjustment prevents power coincidence before it happens.
3Productivity
If the clock continues without suspension, then processing speed is maintained at 100%, but power consumption increases
Solution Approach 1:
The patent applies periodic action by implementing intermittent clock generation with defined continuous periods and idle periods. During continuous periods, the clock operates at full frequency to maintain processing speed. During idle periods, the clock is suspended to eliminate unnecessary power consumption. By repeating this pattern at appropriate ratios (e.g., 3:1 for 75% speed), the system achieves both productivity control and energy loss reduction.
Solution Approach 2:
The patent applies parameter changes by dynamically modifying the clock signal parameters (frequency, duty cycle, presence/absence) based on processing requirements. The clock rate control circuit changes the clock waveform from continuous to intermittent, adjusting the proportion of continuous versus idle periods to match the required processing speed. This parameter modification directly reduces power consumption by eliminating clock signals during periods when full processing capacity is not needed.
Data Source
AI summary
A clock generator includes a counter unit receiving a reference clock signal to generate a timing signal, a selector receiving the timing signal to output a clock enable based on bit string data stored in a storage unit and a clock gate cell receiving the reference clock signal based on the clock, thinning some pulses out from the reference clock signal based on the clock enable so that a clock signal is maskable, and outputting an inter intermittent clock signal.