Internal Clock Frequency Switching for Precise Command Timing
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Solution Overview
Problem
Conventional semiconductor apparatuses face challenges in precisely recognizing and performing operation modes due to variations in command pulse width relative to clock cycles, leading to potential failures in read or write operations.
Innovation Solution
A semiconductor apparatus with a clock frequency change block that generates internal clocks with different frequencies in response to a mode register set signal and a command generation block that synchronizes commands with these internal clocks, ensuring precise timing and mode recognition through a flag signal and frequency change end signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the pulse width of the command CMDB is larger than one cycle of the clock CLK, then the command can be recognized, but the internal command ICMD has different setup/hold time from the pulse width of the command CMDB, causing the semiconductor apparatus to fail to perform operation mode precisely
Solution Approach 1:
The patent applies dynamics by making the internal clock frequency adjustable based on command pulse width. When the command pulse width exceeds one clock cycle, the system dynamically changes the internal clock frequency to match the command duration, ensuring that setup and hold times remain precise regardless of varying command lengths. This is achieved through a frequency change block that receives control signals and adjusts the internal clock accordingly.
Solution Approach 2:
The patent changes the frequency parameter of the internal clock based on the command pulse width. A frequency change end signal is generated to indicate when the frequency adjustment is complete, allowing the system to adapt the clock frequency to match different command durations while maintaining precise timing relationships for setup and hold times.
2Manufacturing precision
If the pulse width of the command CMDB is the same as one cycle of the clock CLK, then the internal command ICMD has the same setup/hold time as the pulse width of the command CMDB, but the system lacks adaptability for commands with different pulse widths
Solution Approach 1:
The system dynamically adjusts the internal clock frequency based on the actual command pulse width. Instead of using a fixed clock frequency, the frequency change block modifies the internal clock frequency to adapt to different command durations, enabling the system to handle various command types while maintaining precise setup and hold times.
Solution Approach 2:
The patent changes the frequency parameter of the internal clock to match different command pulse widths. By receiving control signals that indicate the command duration, the system adjusts the clock frequency parameter accordingly, providing adaptability for commands with different pulse widths while preserving timing precision.
Data Source
AI summary
A semiconductor apparatus includes a clock frequency change block configured to output a plurality of internal clocks with different frequencies by dividing a frequency of an external clock in response to a mode register set signal and a setting command to enable the plurality of internal clocks to be outputted, and generate a flag signal to designate the completion of the output, and a command generation block configured to receive a command and generate the setting command in response to the flag signal and the mode register to set signal.