Internal Clock Generation with Phase-Locked Delay Compensation
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Solution Overview
Problem
High-frequency synchronous semiconductor devices face malfunctions due to delay times in data output synchronization with external clock signals, reducing valid data windows and affecting operation speed.
Innovation Solution
An internal clock generation circuit comprising an interpolation clock generation circuit and a locked clock generation circuit, which generates internal clock signals by comparing phase differences between division clock signals and feedback clock signals, using switching and current control signals to adjust drivability and phase alignment, thereby compensating for internal circuit delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If synchronous semiconductor devices operate at high frequency with external clock signals, then operation speed is improved, but delay time reduces valid data window causing malfunction
Solution Approach 1:
The patent applies preliminary action by generating the internal clock signal in advance before the data output operation. The internal clock generation circuit creates a clock signal that is phase-aligned with the data output timing, allowing the system to prepare for high-frequency operation without suffering from the tAC delay problem. This pre-synchronization enables reliable high-speed operation by eliminating the timing uncertainty that causes malfunctions.
Solution Approach 2:
The patent introduces an intermediary internal clock signal that mediates between the external clock and the data output operation. Rather than directly synchronizing data output with the external clock, the system uses the internally generated clock as an intermediate reference that is specifically timed to account for the tAC delay, thus resolving the contradiction between high speed operation and reliable data window timing.
2Reliability
If internal clock signal phase is adjusted for synchronization, then reliability is improved, but phase alignment precision deteriorates due to jitter
Solution Approach 1:
The patent implements feedback by continuously monitoring the phase relationship between the internal clock signal and the data output signal, and adjusting the internal clock generation accordingly. The phase detector compares the timing of these signals and provides feedback to the delay element, which adjusts the internal clock phase to maintain optimal alignment. This closed-loop control reduces jitter and maintains precise phase alignment, resolving the contradiction between reliability and measurement precision.
Solution Approach 2:
The patent applies dynamics by making the internal clock generation adaptive rather than fixed. The delay element's timing is dynamically adjusted based on real-time phase detection feedback, allowing the system to adapt to varying operating conditions and minimize jitter. This dynamic adjustment mechanism maintains precise phase alignment across different frequencies and loading conditions, improving both reliability and measurement precision.
Data Source
AI summary
An internal clock generation circuit includes an interpolation clock generation circuit and a locked clock generation circuit. The interpolation clock generation circuit generates an interpolation clock signal from a division clock signal in response to a switching control signal and a current control signal. The locked clock generation circuit includes an oscillator and generates a locked clock signal for generating an internal clock signal from the interpolation clock signal.