Internal Clock Buffering with Delayed Enable Synchronization
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Solution Overview
Problem
Conventional semiconductor devices experience glitches in generating internal clock signals due to synchronization issues between external clock signals and clock enable signals, leading to malfunctioning as the frequency of external clock signals increases, especially when the transition times of these signals are close to each other.
Innovation Solution
A clock buffering circuit that includes a clock delay section generating multiple synchronization clock signals with varying delay amounts, a synchronization section synchronizing the clock enable signal with these signals in a specific order, and an internal clock generation section that generates an internal clock signal based on the synchronized clock enable signal, preventing glitches by ensuring precise logic levels and toggling intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single synchronization clock signal is used to synchronize the clock enable signal, then the circuit complexity is low, but glitches occur when the transition times of external clock and clock enable signals are close
Solution Approach 1:
The synchronization clock signal is segmented into multiple signals with different delay amounts (first synchronization clock signal, second synchronization clock signal, etc.). The clock enable signal is synchronized with these segmented signals in a specific order, which prevents glitches by ensuring proper timing relationships without requiring complex synchronization logic.
Solution Approach 2:
The method performs preliminary synchronization actions by first synchronizing the clock enable signal with the first synchronization clock signal (having a larger delay), and then synchronizing the result with the second synchronization clock signal (having a smaller delay). This preliminary action sequence ensures that timing conflicts are avoided before they can cause glitches.
2Productivity
If the external clock frequency is increased to improve processing speed, then productivity increases, but glitches become more likely to occur
Solution Approach 1:
By segmenting the synchronization clock into multiple signals with different delays, the circuit can maintain proper timing relationships even at higher external clock frequencies. The segmented approach creates buffer zones that prevent timing conflicts from occurring as frequency increases.
Solution Approach 2:
The method changes the timing parameters by introducing multiple delay amounts in the synchronization clock signals. This parameter adjustment allows the circuit to maintain stable operation at higher frequencies by ensuring that the clock enable signal transitions are properly aligned with clock edges regardless of frequency variations.
3Ease of manufacture
If simple synchronization is used to reduce circuit complexity, then ease of manufacture improves, but manufacturing precision requirements increase to avoid glitches
Solution Approach 1:
The synchronization clock is segmented into multiple signals with predetermined delay amounts. This segmentation approach simplifies the manufacturing process by using standard delay elements rather than requiring precise timing alignment through complex circuit design, thereby reducing manufacturing precision requirements while maintaining glitch-free operation.
Data Source
AI summary
A semiconductor device includes a clock delay section configured to receive an external clock signal, reflect different delay amounts on the external clock signal, and generate a plurality of synchronization clock signals, a clock synchronization section configured to synchronize a clock enable signal with each of the plurality of synchronization clock signals in an order beginning with a synchronization clock signal, on which a largest delay amount is reflected, to a synchronization clock signal, on which a smallest delay amount is reflected, and to generate a synchronized clock enable signal, and an internal clock generation section configured to generate an internal clock signal corresponding to the external clock signal, and to be on/off controlled in its operation in response to the synchronized clock enable signal.