Internal Clock Control Circuit for Low-Power Ferroelectric Data Hold
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Solution Overview
Problem
Conventional data hold devices using ferroelectric elements face issues such as high power consumption, data loss due to supply voltage fluctuations, and complex manufacturing processes, along with the need for external clock signals and increased part numbers, which lead to increased electricity consumption and costs.
Innovation Solution
A control circuit with an internal clock generating portion and a control portion that uses internal and external clock signals to perform processing, including a loop structure and filter components, to manage the ferroelectric elements and reduce power consumption by optimizing the operation of the data hold device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If ferroelectric element is used to hold data non-volatilely, then data retention after power off is improved, but power consumption increases due to the ferroelectric element becoming a huge load capacitor
Solution Approach 1:
The patent divides the data hold device into two independent parts: a volatile data hold circuit (latch circuit) and a non-volatile storage element (ferroelectric element). The volatile circuit handles frequent data operations with low power consumption, while the non-volatile element only activates during power loss events to preserve data, thus avoiding the continuous power consumption burden of using solely a ferroelectric-based data hold device.
2Reliability
If ferroelectric element is used for non-volatile storage, then data loss during power cut is prevented, but device complexity increases due to additional control circuits and clock signals
Solution Approach 1:
The patent employs a detection circuit that automatically monitors the power supply voltage and autonomously determines when power loss occurs. Upon detection, the control circuit automatically activates the ferroelectric element to save data, eliminating the need for external control signals or complex clock management. This self-service mechanism simplifies the overall device complexity while ensuring reliable data preservation during power interruptions.
3Use of energy by moving object
If conventional data hold device is used, then power consumption is lower, but data is lost when power is cut off
Solution Approach 1:
The patent implements a periodic monitoring mechanism where the detection circuit continuously checks the power supply voltage at regular intervals. When power loss is detected, the system periodically activates the ferroelectric element to preserve data. This periodic action approach ensures data reliability during power interruptions while minimizing power consumption by keeping the system in a low-power state during normal operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution decreases part numbers and electricity consumption while maintaining data integrity and reducing power usage, allowing for efficient data storage and retrieval without external clock signals, thus improving the overall performance and cost-effectiveness of the data hold device.
Implementation Method 1
the voltage of the signal lines is used to set the residual polarization state of the ferroelectric element CL to write data to the ferroelectric element CL. Data can be held in a non-volatile manner even after power off by such write action.
Implementation Method 2
the node N generates a voltage signal corresponding to the residual polarization state of the ferroelectric element CL. The voltage signal generated by node N perform data determination (0/1 determination) according to threshold of the inverter INVx.
Data Source
AI summary
A control circuit 10 includes an internal clock generating portion (12), which starts generating an internal clock signal (LCLK) required by a control portion (11) to perform action when a specific signal pattern appears in a trigger signal, continually generates the internal clock signal (LCLK) at least before the control portion (11) completes predetermined processing, and then stops generating the internal clock signal (LCLK); and the control portion (11), which uses the internal clock signal (LCLK) to perform the predetermined processing.