Internal Clock Synchronization for Asynchronous Memory Signals
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Solution Overview
Problem
In high-speed memory devices like DDR SDRAM, synchronizing asynchronous signals without an external system clock is challenging due to power consumption issues and inefficiencies in using a constant external clock, especially in portable devices where power is limited and external clocks may not be available.
Innovation Solution
An asynchronous synchronization device generates an internal clock signal upon receiving asynchronous input signals, allowing for synchronization without an external clock, using staging circuitry, latching circuitry, and an internal clock generator to produce a temporary internal clock for synchronizing signals, which is then disabled once synchronization is achieved.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an external system clock is used to synchronize signals, then signal alignment is ensured, but power consumption increases
Solution Approach 1:
The invention extracts the clock generation function from the external system and implements it internally within the memory device. The internal clock generator produces clock signals locally, eliminating the need for a constant external clock signal while maintaining synchronization capability. This is achieved by incorporating a phase detector, delay element, and inverter that work together to generate internal clock signals based on detected phase differences.
Solution Approach 2:
The invention implements dynamic clock signal generation where the internal clock frequency and phase are adjusted based on detected phase differences between external and internal signals. The system transitions from a static external clock dependency to a dynamic internal clock generation that adapts to signal alignment requirements, enabling the clock to be generated only when needed rather than continuously.
2Reliability
If an external system clock is continuously provided, then signal synchronization is maintained, but power efficiency decreases
Solution Approach 1:
Instead of continuous external clock signaling, the invention implements periodic internal clock generation triggered by phase detection events. The internal clock generator activates only when phase alignment is needed, creating clock signals periodically rather than continuously. This reduces power consumption by eliminating the constant presence of external clock signals while maintaining synchronization when required.
Solution Approach 2:
The memory device serves itself by generating internal clock signals rather than relying on continuous external clock provision. The phase detector detects phase differences and the internal clock generator automatically produces the necessary clock signals to maintain synchronization, making the system self-sufficient and eliminating the need for continuous external power delivery through clock signals.
3Reliability
If external clock is used for asynchronous signals, then clock domain alignment is achieved, but power consumption increases inefficiently
Solution Approach 1:
The invention segments the clock generation function into separate components: an external clock interface, a phase detector, a delay element, and an internal clock generator. This segmentation allows the system to handle synchronous and asynchronous signals differently, generating internal clock signals only when needed for asynchronous operations rather than using a single external clock for all signals, thereby improving power consumption efficiency.
Data Source
AI summary
One or more techniques are provided for the synchronization of asynchronous signals without the use of an external system clock. In one embodiment, an asynchronous synchronization device is provided and configured to synchronize one or more asynchronous signals to an internal clock signal provided by an internal clock generator. The internal clock generator may be enabled upon detecting inputs on the one or more asynchronous signals, and disabled once the one or more asynchronous inputs are synchronized with the internal clock signal. Thus, the internal clock signal is provided only for a duration required to synchronize the one or more asynchronous signals. Embodiments of the asynchronous synchronization device, as disclosed herein, may be implemented in a processor-based device and/or a memory device.