Internal Clock Selection for PVT-Compensated Memory Timing
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Solution Overview
Problem
Ferroelectric memory devices in integrated circuits exhibit non-tracking behavior with variations in process, voltage, and temperature, leading to mismatched switching behavior with CMOS circuits, resulting in weakened read signals and slower operation at cold temperatures, which complicates clock signal generation and memory access.
Innovation Solution
Implementing a plurality of internal clock circuits operating at different frequencies, with the lowest-frequency circuit selected based on current operating conditions to ensure reliable clock signal generation and memory access across varying parameters, optimizing chip area usage without reducing memory availability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single internal clock circuit is used, then the circuit complexity is low, but the timing reliability varies significantly (up to 100%) across process, voltage, and temperature corners
Solution Approach 1:
The internal clock generation is segmented into multiple independent clock circuits (e.g., first internal clock circuit and second internal clock circuit) operating at different frequencies. Each clock circuit is independently evaluated against the system clock to determine suitability, allowing the system to select the most appropriate clock source for current operating conditions, thereby improving timing reliability without requiring a single complex adaptive circuit.
Solution Approach 2:
The clock circuit selection is made dynamic based on real-time operating conditions. The system measures the number of cycles of internal clock circuits against the system clock and selectively enables the appropriate internal clock circuit based on current process, voltage, and temperature conditions. This dynamic adaptation ensures optimal timing reliability across varying operating corners.
2Reliability
If multiple internal clock circuits are implemented, then timing reliability across PVT corners improves, but the chip area increases
Solution Approach 1:
Instead of one large complex clock circuit, the solution segments clock generation into multiple simpler clock circuits operating at different frequencies. This segmentation achieves better PVT coverage through diversity while using less total area than a single highly complex adaptive clock circuit would require.
Solution Approach 2:
Multiple clock circuits are designed with different operating frequencies and characteristics to cover different process, voltage, and temperature corners. By changing the frequency parameter across multiple simple circuits rather than making one circuit highly complex, the solution achieves broad PVT coverage with minimal area overhead.
3Productivity
If the highest frequency internal clock is always selected, then productivity is maximized, but reliability at cold temperature corners deteriorates due to non-tracking behavior
Solution Approach 1:
The system dynamically selects which internal clock circuit to use based on measured performance against the system clock and current operating conditions. Rather than always using the highest frequency clock, the system adapts its clock selection to ensure reliable operation across temperature corners, switching to appropriate frequency clocks as conditions require.
Solution Approach 2:
The system implements feedback by measuring the number of cycles of internal clock circuits against the system clock over multiple cycles. This measurement feedback is used to determine which internal clock circuit is suitable for current conditions, ensuring that productivity is maximized only when reliability conditions are met, particularly at cold temperature corners where ferroelectric memory tracking behavior degrades.
4Reliability
If additional delay is added to compensate for cold temperature operation, then reliability at cold corners improves, but productivity at high temperature corners decreases
Solution Approach 1:
Instead of adding uniform delay to all clock signals, the solution segments clock generation into multiple circuits with inherently different frequencies. Each clock circuit is designed to naturally accommodate different temperature conditions without requiring additional compensating delay, thus avoiding productivity loss at high temperature corners while maintaining reliability at cold corners.
Data Source
AI summary
An integrated circuit including a plurality of internal clock generator circuits from which an internal clock is selected based on an external time reference. A number of cycles of internal clock signals from each of the internal clock generator circuits, or from at least one of those circuits where a frequency relationship is known, is counted relative to a system clock signal based on the external time reference. The lowest frequency internal clock signal providing at least a minimum number of cycles within the system clock period, the minimum number assuring completion of a function within a time constraint, is selected as the internal clock. Robust performance over a wide range of fabrication process parameters and operating conditions is assured.