Internal Clock Synchronization for Asynchronous Memory Signals
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Solution Overview
Problem
In high-speed memory devices like DDR SDRAM, synchronizing asynchronous signals without an external system clock is challenging due to power constraints and inefficiencies in using a constant external clock, especially in portable devices where power is limited and external clocks may not be available.
Innovation Solution
An asynchronous synchronization device generates an internal clock signal upon receiving asynchronous input signals, allowing for synchronization of these signals without relying on an external clock, using staging circuitry, latching circuitry, and a synchronization circuit to align the signals with an internal clock, which is then disabled once synchronization is achieved.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an external system clock is used to synchronize signals, then signal alignment is ensured, but power consumption increases
Solution Approach 1:
The invention extracts the clock generation function from the external system and implements it internally within the memory device. The internal clock generator produces clock signals locally, eliminating the need for a constant external clock signal while maintaining synchronization capability through the delay-locked loop circuitry.
Solution Approach 2:
Instead of using a continuous external clock signal, the invention employs periodic internal clock generation triggered by specific events (such as write commands). The internal clock is activated only when needed for synchronization operations and can be placed in low-power states otherwise, reducing overall power consumption while maintaining signal alignment when required.
2Reliability
If an external system clock is continuously running, then signal synchronization is maintained, but power efficiency decreases
Solution Approach 1:
The invention makes the clock system dynamic by implementing an internal clock generator that can be selectively enabled and disabled based on operational requirements. The delay-locked loop circuit dynamically adjusts phase and frequency of internal clock signals to maintain synchronization with external signals only when needed, allowing the system to transition between active and low-power states efficiently.
Solution Approach 2:
The invention changes the operational parameters of the clock system by using an internal clock generator that can be controlled to operate only during specific periods or conditions. The delay-locked loop dynamically adjusts clock phase and frequency parameters to achieve synchronization without requiring a continuously running external clock, thereby improving power efficiency while maintaining synchronization capability when required.
Data Source
AI summary
One or more techniques are provided for the synchronization of asynchronous signals without the use of an external system clock. In one embodiment, an asynchronous synchronization device is provided and configured to synchronize one or more asynchronous signals to an internal clock signal provided by an internal clock generator. The internal clock generator may be enabled upon detecting inputs on the one or more asynchronous signals, and disabled once the one or more asynchronous inputs are synchronized with the internal clock signal. Thus, the internal clock signal is provided only for a duration required to synchronize the one or more asynchronous signals. Embodiments of the asynchronous synchronization device, as disclosed herein, may be implemented in a processor-based device and/or a memory device.