Internal Clock Duty Control During Semiconductor Startup
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Solution Overview
Problem
Semiconductor integrated circuits face challenges in generating stable internal clocks for semiconductor memory, particularly during power instability, which can lead to erroneous data latching due to insufficient setup and hold times.
Innovation Solution
Incorporating a detection circuit and generation circuit with a variable register to delay the detection of the reference delay amount until the reference clock is stable, and using time averaging and limit setting to optimize the internal clock generation, ensuring accurate phase control and duty ratio adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the detection circuit detects the reference delay amount immediately when the first clock is input, then the internal clock generation speed is improved, but the clock stability deteriorates due to power instability during startup
Solution Approach 1:
The invention applies preliminary action by implementing a warm-up period before the detection circuit starts detecting the reference delay amount. During this warm-up period, the system allows the power supply voltage to stabilize before beginning clock detection, ensuring that the detected reference delay amount is accurate and not affected by power instability. This preliminary stabilization action resolves the contradiction by sacrificing initial detection speed to ensure long-term clock stability.
2Stability of the object's composition
If the detection circuit starts detecting reference delay amount after a warm-up period, then the clock stability is improved, but the internal clock generation time is increased
Solution Approach 1:
The invention applies parameter changes by dynamically adjusting the detection start timing based on the warm-up period duration. The system changes the temporal parameter of when detection begins, optimizing it to start after power stabilization. This allows the system to balance between stability improvement and time loss by precisely controlling the detection start point rather than using a fixed delay.
3Device complexity
If the system uses a fixed detection timing for reference delay amount, then the circuit complexity is reduced, but the adaptability to power variations deteriorates
Solution Approach 1:
The invention applies dynamics by making the detection start timing variable rather than fixed. The detection circuit is designed to begin operation after a predetermined warm-up period, making the detection timing adaptive to power supply conditions. This dynamic approach allows the system to handle power variations during startup without requiring complex voltage regulation circuits, thus maintaining relatively simple circuitry while improving adaptability.
Data Source
AI summary
A semiconductor integrated circuit includes a register, a detection circuit, and a generation circuit. The register stores a detection start timing of a reference delay amount based on a first clock during a first period. The first period is a period in which the first clock starts to be input. The detection circuit has a plurality of delay stages. The detection circuit detects the reference delay amount at the start timing during the first period and obtains the number of delay stages corresponding to the reference delay amount. The generation circuit adjusts a duty ratio of the first clock based on the number of delay stages obtained by the detection circuit and generates a second clock during a second period. The second period is a period continuing from the first period.