Internal Command Timing Compensation in Semiconductor Clock Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices face challenges in efficiently controlling signal transmission and generation timing of internal commands, leading to increased area and current consumption in shifting circuits.
Innovation Solution
A semiconductor device and system that includes a frequency division circuit to generate division clocks and an internal command generation circuit to latch and compensate for the generation timing of internal commands using phase detection signals, reducing the need for multiple shifting circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple shifting circuits are used to shift commands using multiple division clocks, then internal commands can be generated for performing internal operations, but the area and current consumption increase
Solution Approach 1:
The patent merges multiple shifting circuits into a single shifting circuit by combining the phase detection signals from multiple division clocks into one unified signal path. This allows the single circuit to handle commands from multiple division clocks (first division clock and second division clock) without requiring separate shifting circuits for each, thereby reducing area while maintaining the capability to generate internal commands for various internal operations.
Solution Approach 2:
The single shifting circuit is designed to be universal by accepting phase detection signals from multiple division clocks and generating appropriate internal commands for different internal operations. The circuit can shift commands based on either the first division clock or the second division clock, making it multi-functional rather than requiring dedicated circuits for each clock domain.
2Productivity
If multiple shifting circuits are used to shift commands using multiple division clocks, then internal commands can be generated for performing internal operations, but current consumption increases
Solution Approach 1:
The patent merges multiple shifting circuits into a single shifting circuit by combining the phase detection signals from multiple division clocks into one unified signal path. This allows the single circuit to handle commands from multiple division clocks (first division clock and second division clock) without requiring separate shifting circuits for each, thereby reducing area while maintaining the capability to generate internal commands for various internal operations.
Solution Approach 2:
The single shifting circuit is designed to be universal by accepting phase detection signals from multiple division clocks and generating appropriate internal commands for different internal operations. The circuit can shift commands based on either the first division clock or the second division clock, making it multi-functional rather than requiring dedicated circuits for each clock domain.
3Device complexity
If phase detection signals are not latched in pipe latches, then circuit complexity is reduced, but timing compensation for internal command generation cannot be achieved
Solution Approach 1:
The patent applies preliminary action by latching the phase detection signal in the pipe latch before it is used for timing compensation. This advance latching ensures that the timing information is captured and stabilized prior to being used by the shifting circuit to generate internally timed commands, thereby achieving precise timing compensation without adding significant complexity to the overall circuit architecture.
Data Source
AI summary
A semiconductor device includes a frequency division circuit configured to generate a first division clock and a second division clock by dividing a frequency of a clock, and an internal command generation circuit configured to generate an internal command based on a command in synchronization with the first division clock and the second division clock, configured to latch, in a pipe latch, a phase detection signal that is generated based on the timing at which the command is received, and configured to compensate for generation timing of the internal command based on the phase detection signal that has been latched in the pipe latch.


