Internal Conductive Line Characterization for Cell Timing and Power
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Solution Overview
Problem
Existing design processes for semiconductor integrated circuits (ICs) are inadequate in accurately accounting for variations in internal nets, leading to overestimation of timing and power performance and unnecessary area and power wastage due to non-selective timing and power budgets.
Innovation Solution
An improved cell characterization method that identifies critical internal nets within cells and updates cell libraries to include timing and power parameters based on these nets, using a multidimensional input set to refine estimates and reduce overestimation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If non-selective timing and power budgets are applied to all internal nets, then design simplicity is maintained, but timing and power estimation accuracy deteriorates
Solution Approach 1:
The patent segments internal nets into critical and non-critical categories based on their proximity to cell boundaries. Critical internal nets are those within a threshold distance from the cell boundary, while others are non-critical. This segmentation allows selective characterization - detailed timing and power analysis is performed only on critical nets, while non-critical nets use simplified models. This resolves the contradiction by applying complexity only where necessary (near boundaries) while maintaining simplicity elsewhere.
Solution Approach 2:
The patent applies different characterization qualities to different regions of the cell. Local quality analysis is performed on internal nets near cell boundaries where timing and power variations are most significant. The characterization parameters (timing, power, area) are adjusted locally based on the net's position and criticality. This allows high accuracy where needed (at boundaries) while maintaining overall design efficiency.
2Measurement precision
If critical internal nets are identified and characterized selectively, then timing and power estimation accuracy is improved, but design process complexity increases
Solution Approach 1:
The patent performs preliminary identification and characterization of critical internal nets during the cell design phase. By pre-determining which nets are critical and preparing their characterization data in advance, the design process avoids repetitive complex analysis during later stages. This preliminary action streamlines the overall design flow while maintaining high accuracy for critical paths.
Solution Approach 2:
The cell characterization process automatically identifies critical internal nets and applies appropriate characterization parameters without requiring manual intervention. The system self-determines which nets need detailed analysis based on their geometric properties and automatically adjusts timing and power estimates accordingly. This automation maintains design efficiency while achieving high measurement precision.
Data Source
AI summary
A method including: providing a design data of an integrated circuit (IC), the design data including a first cell; identifying a first conductive line in the first cell as a critical internal net of the first cell, wherein the first conductive line is determined as being close to a cell boundary of the first cell; providing a library of the first cell, wherein the library includes a table of timing parameters or power parameters of the first cell associated with different configurations; updating the design data by determining a timing or power value of the first cell based on the table; performing a timing analysis on the updated design data; and forming a photomask based on the updated design data in response to determining that the timing analysis of the updated design data complies with a specification.