Internal Host Bus Bridge Architecture for Multi-Processor Systems
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Solution Overview
Problem
Conventional multi-GPU systems face inefficiencies in data transfer due to shared bandwidth requirements, particularly in systems where graphics processing units (GPUs) need significant bandwidth for data-intensive applications, leading to a desire for an architecture that reduces components while maintaining efficient data transfer.
Innovation Solution
The implementation of an internal host bus bridge architecture where multiple bus endpoints are coupled to a bus root via an internal host bus bridge, allowing direct coupling between endpoints and eliminating the need for an external bridge, enabling peer-to-peer transactions on the same wires as endpoint-to-root transactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If an external bridge is used to connect multiple GPUs to the host, then the system can achieve peer-to-peer data transfer between GPUs, but the shared bandwidth between peer-to-peer traffic and host traffic reduces data transfer efficiency
Solution Approach 1:
The patent embeds the bridge functionality directly inside the GPU endpoints rather than using a separate external bridge. Each GPU contains an internal bridge that handles peer-to-peer transactions locally, nesting the bridging function within the endpoint devices themselves. This eliminates the need for a separate external bridge component while maintaining the ability to route transactions between GPUs and the host.
Solution Approach 2:
The patent extracts the bridge function from the external host interface and relocates it into the GPU endpoints. By taking out the bridging capability from the shared external bridge and placing it within each GPU, the system enables dedicated peer-to-peer transaction paths that do not contend with host traffic for bandwidth.
2Device complexity
If multiple GPUs share a common host interface, then the system architecture is simplified, but the shared bandwidth causes bottlenecks in data-intensive graphics applications
Solution Approach 1:
The patent segments the transaction paths by creating separate logical channels for peer-to-peer GPU communication and host communication. Each GPU's internal bridge can independently handle peer-to-peer transactions without requiring them to share the physical bandwidth with host transactions, effectively segmenting the bandwidth allocation.
Solution Approach 2:
The patent adds a dimensional layer to the transaction routing by implementing internal bridges within each GPU that create a secondary transaction path. This allows peer-to-peer transactions to occur through an alternative route (via internal bridges) rather than forcing all traffic through the single external host interface dimension.
3Productivity
If an internal host bus bridge is implemented within each GPU, then peer-to-peer data transfer efficiency is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The internal bridge structure is designed as a universal component that handles multiple types of transactions (peer-to-peer and host communications) through a standardized interface. This multi-functional design allows the same internal bridge architecture to be used across different GPU models, simplifying manufacturing despite the added functionality.
Data Source
AI summary
An internal bus architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols.