Internal Jitter Tolerance Tester with PRBS Generator
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current jitter tolerance testing methods are inadequate for accurately simulating real-world random noise in serial links, as they rely on sinusoidal models despite actual jitter patterns being more like random noise, and lack efficient means to generate and control accumulated jitter in laboratory settings.
Innovation Solution
An internal jitter tolerance tester with a loop filter, an internal jitter generator, a gain multiplier, and a phase rotator controller, utilizing a pseudorandom binary sequence generator, lowpass filter, and gain controller to produce and control accumulated jitter, as well as a sinusoid jitter generator with adjustable frequency and amplitude, and a digitally controlled oscillator to simulate various jitter conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sinusoidal jitter models are used for testing, then jitter tolerance specification can be defined and measured, but the testing does not accurately reflect real-world random noise conditions in serial links
Solution Approach 1:
The patent changes the fundamental parameter of jitter waveform from sinusoidal to pseudorandom binary sequence (PRBS) based random noise. This allows the test to simultaneously achieve measurement precision through controlled injection of known jitter patterns while improving adaptability by accurately simulating real-world serial link conditions where jitter manifests as random noise rather than pure sinusoids
2Measurement precision
If internal jitter generation is implemented, then accumulated jitter can be controlled and measured, but the device complexity increases with additional components
Solution Approach 1:
The patent merges the jitter generation functionality directly into the CDR tester device by integrating a PRBS generator, accumulator, and loop filter within the same device. This combination allows accumulated jitter to be generated and controlled internally without requiring separate external jitter injection equipment, thereby achieving precise accumulated jitter measurement while managing device complexity through functional integration
Solution Approach 2:
The CDR tester performs self-testing by generating its own accumulated jitter through internal PRBS sequences that are accumulated and filtered, then injecting these self-generated jitter signals back into the system. This self-service approach enables controlled accumulated jitter measurement without external test equipment, balancing measurement precision with acceptable device complexity
Data Source
AI summary
Exemplary embodiments of the present invention relate to an internal jitter tolerance tester. The internal jitter tolerance tester may include a digital loop filter consisting of a cyclic accumulator which accumulates a phase detector's output, a gain multiplier, an internal accumulated jitter generator (or an internal sinusoid jitter generator), and a phase rotator (or DCO) controller.The internal accumulated jitter generator may include a PRBS generator, a digital loop filter, an accumulator, and a gain controller. The accumulated jitter generator also may be replaced with the internal sinusoid jitter generator. The internal sinusoid jitter generator may include a counter, a sinusoid jitter profile lookup table, and a gain controller.