Internal Latch Circuit Using Edge-Triggered D Flip-Flops
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Solution Overview
Problem
The stability of write operations in double data rate SDRAM is compromised due to variations in the delay time tDQSS of the input delay signal caused by temperature and manufacturing technology, leading to incorrect latch signal generation and unstable performance.
Innovation Solution
An internal latch circuit utilizing a combination of low and high initial value D flip-flops to generate internal input signals based on the data strobe signal and input delay signal, with a NAND gate to produce a stable latch signal, thereby isolating the influence of tDQSS on the latch signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the internal latch circuit uses conventional delay signal processing, then the circuit structure is simple, but the latch signal generation is incorrect when delay time varies, causing unstable write operation performance
Solution Approach 1:
The patent segments the delay signal processing into multiple independent D flip-flop stages (first and second D flip-flops for each data line). Each flip-flop captures the delay signal at specific clock edges, breaking down the complex timing relationship into manageable discrete stages that are less sensitive to overall delay variations.
Solution Approach 2:
The patent employs dynamic clocking where different D flip-flops are triggered by different clock edges (rising and falling edges). This dynamic approach allows the circuit to adapt to delay variations by selectively capturing signals at appropriate timing moments, ensuring stable latch signal generation despite tDQSS fluctuations.
2Reliability
If the delay time tDQSS is held constant, then the latch signal generation is stable, but temperature and manufacturing variations cause tDQSS to change, leading to performance degradation
Solution Approach 1:
The patent implements a feedback mechanism where the D flip-flops continuously sample the delay signal WR_LAT_P1 against the clock signal edges. This feedback loop automatically adjusts the captured timing by leveraging the inherent clock signal structure, compensating for delay variations without requiring external calibration or adjustment mechanisms.
Solution Approach 2:
The patent changes the temporal parameters of signal capture by using both rising and falling edges of the clock signal. This parameter transformation converts a static delay problem into a dynamic sampling process, where the effective sampling points shift with delay variations, maintaining accurate latch signal generation across different environmental conditions.
3Measurement precision
If the circuit responds to both rising and falling edges of the delay signal, then more timing information is captured, but the latch signal becomes incorrect due to edge variations
Solution Approach 1:
The patent introduces asymmetry in the clock signal utilization by assigning different functions to rising and falling edges. The first D flip-flop captures on one edge while the second captures on the opposite edge, creating an asymmetric sampling pattern that selectively extracts valid timing information while filtering out erroneous transitions caused by delay variations.
Data Source
AI summary
An internal latch circuit having a plurality of low initial value D flip-flops, a plurality of high initial value D flip-flops, an internal latch signal generating circuit and a NAND gate, and a method for generating latch signal thereof is provided. First, an input delay signal in response to a clock signal is generated. Then, a first internal input signal, a first reverse internal input signal, a second internal input signal, and a second reverse internal input signal are generated by using the low initial value D flip-flops and the high initial value D flip-flops, based on the internal data strobe signal and in response to the input delay signal, and are transmitted to the internal latch signal generating circuit. Then, the internal latch signal generating circuit outputs the first reverse pre-output signal and the second reverse pre-output signal. Finally, an internal latch signal is generated through a NAND gate.