Internal Load Reference Circuit for IC Pin Short Detection
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Solution Overview
Problem
Integrated circuit (IC) pins face damage and operational interference due to pin shorts, which occur when insufficiently resistive loads cause excessive current flow, and existing technologies lack effective detection and mitigation mechanisms to prevent damage and maintain functionality according to certification standards.
Innovation Solution
The implementation of a device with a comparison circuit that monitors the voltage at an external load node against a proportionately configured internal load node, generating an alert signal when a short circuit is detected, and utilizing a voltage offset circuit and de-glitch circuit to mitigate errors and temporal fluctuations, ensuring reliable detection and prevention of damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pin short detection mechanisms are implemented, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent creates a simplified copy of the output driver circuitry inside the IC package, including a replica driver and replica load that mimics the external load characteristics. This internal copy generates a reference signal that can be compared against the actual output signal to detect pin shorts without requiring complex external monitoring equipment.
Solution Approach 2:
The patent introduces an intermediary comparison circuit that compares the reference signal from the internal replica circuitry with the actual output signal. This intermediary mechanism enables detection of pin short conditions by identifying discrepancies between expected and actual signal behavior, providing reliable detection while maintaining manageable circuit complexity.
2Measurement precision
If accurate pin short detection is implemented, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent creates a simplified copy of the output driver circuitry inside the IC package, including a replica driver and replica load that mimics the external load characteristics. This internal copy generates a reference signal that can be compared against the actual output signal to detect pin shorts without requiring complex external monitoring equipment.
Solution Approach 2:
The patent configures the replica driver and replica load with proportional sizing relationships that create equipotential conditions during normal operation. The replica load is sized proportionally to the external load, and the replica driver is sized proportionally to the output driver, ensuring that voltages at corresponding nodes remain equal under normal conditions, which simplifies the detection logic.
3Measurement precision
If proportional sizing of internal load and driver is implemented, then detection accuracy is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent configures the replica driver and replica load with proportional sizing relationships that create equipotential conditions during normal operation. The replica load is sized proportionally to the external load, and the replica driver is sized proportionally to the output driver, ensuring that voltages at corresponding nodes remain equal under normal conditions, which simplifies the detection logic.
Solution Approach 2:
The patent employs parameter changes by establishing proportional relationships between the replica components and the actual output components. Rather than requiring exact copies, the patent allows the replica components to be scaled versions with consistent proportional relationships, which maintains detection accuracy while relaxing manufacturing precision requirements.
Data Source
AI summary
In some examples, a device comprises a first driver coupled to a first node, the first node to couple to a first load external to the device. The device comprises a second driver coupled to a second node, the second node coupled to a second load internal to the device. The device comprises a comparison circuit having an inverting input coupled to the first node and a non-inverting input coupled to the second node. Sizes of the second driver and the second load are configured proportionately to sizes of the first driver and the first load, respectively.