Internal Power Supply Voltage Generation Circuit for Deep Power-Down Reset

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Solution Overview

Problem

Conventional semiconductor memory devices face challenges in ensuring complete reset of internal circuits during deep power-down (DPD) exit mode due to short transition times for internal power supply voltage generation, leading to incomplete reset of internal circuits.

Innovation Solution

A circuit and method that generate an internal power supply voltage with a pre-processing unit, a generating unit, and an initialization signal unit, which define a transition time for the internal power supply voltage, ensuring stable voltage generation and complete reset of internal circuits by using a feedback circuit with NMOS transistors having higher threshold voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If the internal power supply voltage is generated using a conventional method with external initialization signal, then the transition time for voltage generation is short, but the internal circuits cannot be completely reset during DPD exit mode

Engineering Contradiction:
Improvetransition time for voltage generationVSAvoidcomplete reset of internal circuits
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The power supply voltage generation is divided into two distinct stages: a pre-processing stage that generates an initial voltage with extended transition time for complete circuit reset, and a main generation stage that provides stable voltage. This segmentation allows each stage to optimize for its specific function, resolving the contradiction between fast transition and complete reset.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The pre-processing unit performs preliminary voltage generation before the main power supply unit activates. This preliminary action extends the transition time to ensure all internal circuits are completely reset during DPD exit mode, preventing incomplete reset issues that occur in conventional single-stage generation.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the transition time for internal power supply voltage is extended to ensure complete reset, then the hold time for initialization signal increases, but the voltage generation speed decreases

Engineering Contradiction:
Improvecomplete reset of internal circuitsVSAvoidvoltage generation speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The voltage generation process is segmented into pre-processing and main generation phases. The pre-processing phase uses extended transition time to ensure complete reset, while the main generation phase uses the power supply voltage generator to quickly establish stable voltage, thus maintaining overall speed while ensuring reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The pre-processing unit and power supply voltage generator operate in continuous sequence without interruption. The pre-processing unit extends the transition time for complete reset, and immediately afterward the power supply voltage generator takes over to maintain stable voltage, ensuring continuous useful action throughout the voltage establishment process.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS8151123B2Circuit and method for generating an internal power supply voltage
Publication Date: 2012.04.03 SAMSUNG ELECTRONICS CO LTD
  • US8151123B2 patent drawing
  • US8151123B2 patent drawing
  • US8151123B2 patent drawing

AI summary

A circuit and method for generating an internal power supply voltage are disclosed. The circuit includes an internal power supply voltage pre-processing unit configured to generate a first internal power supply voltage in response to an external power supply voltage in a power-up mode and a deep power-down (DPD) exit mode to provide the first internal power supply voltage to an output node, and further configured to define a transition time for the first internal power supply voltage, an internal power supply voltage generating unit configured to generate a stable second internal power supply voltage in response to the external power supply voltage to provide the second internal power supply voltage to the output node, and an initialization signal generating unit configured to generate an internal initialization signal in response to the first internal power supply voltage and the second internal power supply voltage.