Internal Stacked Chips in Circuitized Substrates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for forming laminate circuitized substrates, such as PCBs, are time-consuming and inefficient due to the need for precise drilling of multiple thru-holes, which complicates the formation of complex circuitry with increased operational requirements, especially in highly dense PCBs with many layers and small feature sizes.
Innovation Solution
A circuitized substrate assembly is created with two or more semiconductor chips integrally formed within the substrate's multilayered structure, allowing for effective coupling to conductive layers and external components, using known PCB manufacturing processes with minimal modification, and featuring a unique configuration that reduces signal noise and impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to form laminate circuitized substrates with multiple thru-holes, then electrical connections between layers are achieved, but the manufacturing process becomes time-consuming and complex
Solution Approach 1:
The substrate is divided into multiple layers with conductive traces formed on each layer. Instead of drilling thru-holes through the entire substrate thickness, the connection path is segmented into multiple short segments, each formed on a separate layer, reducing the need for deep drilling and plating operations.
Solution Approach 2:
The patent transitions from vertical thru-hole connections to lateral surface-mounted connections. Conductive traces are routed along the surface of the substrate rather than through its thickness, changing the connection dimension from depth (z-axis) to surface (x-y plane), thereby eliminating the need for thru-hole drilling and plating.
2Adaptability or versatility
If the number of layers and circuit density are increased to meet operational requirements, then functional capabilities are enhanced, but the drilling and formation of complex circuitry becomes even more time-consuming
Solution Approach 1:
Conductive traces and connection paths are pre-formed on each substrate layer before assembly. The routing patterns are established in advance during PCB fabrication, allowing for complex multi-layer circuits to be created without requiring time-consuming post-assembly drilling and wiring operations.
Solution Approach 2:
The patent replaces mechanical drilling and plating operations with photolithographic and etching processes. Conductive traces are formed through photoresist patterning and chemical etching rather than mechanical drilling, significantly reducing manufacturing time and complexity for high-density circuits.
3Area of stationary object
If surface space is reduced to accommodate higher density, then compactness is achieved, but signal transmission quality and impedance control become more difficult
Solution Approach 1:
The substrate incorporates locally optimized trace geometries and spacing to maintain controlled impedance in high-density regions. Different areas of the substrate can have different trace widths, spacing, and dielectric thicknesses tailored to specific signal requirements, allowing compact layouts while maintaining signal integrity.
Solution Approach 2:
The patent uses composite substrate structures with multiple dielectric layers and embedded conductive planes. This layered composite structure provides both mechanical support and electrical functionality, enabling compact high-density routing while maintaining controlled impedance through carefully designed dielectric properties and layer configurations.
Data Source
AI summary
A circuitized substrate assembly comprised of at least two circuitized substrates each including a thin dielectric layer and a conductive layer with a plurality of conductive members as part thereof, the conductive members of each substrate being electrically coupled to the conductive sites of a semiconductor chip. A dielectric layer is positioned between both substrates and the substrates are bonded together, such that the chips are internally located within the assembly and oriented in a stacked orientation. A method of making such an assembly is also provided, as is an electrical assembly utilizing same and an information handling system adapted for having such an electrical assembly as part thereof.