Internal Vertical Interconnect Structure for Semiconductor Package
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Solution Overview
Problem
The existing semiconductor packages face challenges in achieving thinner profiles and uniform propagation delays due to the use of bond wires, which require loop height control and result in uneven wire lengths causing timing issues in high-speed applications.
Innovation Solution
The semiconductor device employs an internal vertical interconnect structure using a first conductive layer, an insulating layer with a sloped contour, and a second conductive layer with bumps to provide vertical electrical interconnects, eliminating the need for bond wires and allowing for thinner packages with even propagation delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bond wires are used to interconnect stacked packages, then electrical connection between packages is achieved, but package thickness increases and propagation delays become uneven
Solution Approach 1:
The patent removes bond wires from the interconnection structure entirely, replacing them with an internal vertical interconnect structure formed within the package substrate. This extraction eliminates the loop height control requirement and associated thickness issues while maintaining electrical connectivity between stacked packages.
Solution Approach 2:
The invention transitions from horizontal bond wire connections to vertical internal interconnect structures. By changing the dimensionality of the connection path from lateral (bond wires spanning between packages) to vertical (interconnects formed within the package substrate), the package thickness is reduced while maintaining electrical connection reliability.
2Reliability
If bond wires are used to interconnect stacked packages, then electrical connection is established, but propagation delays become uneven causing timing issues
Solution Approach 1:
The patent eliminates bond wires from the system, removing the source of propagation delay variations. The internal vertical interconnect structure provides uniform current paths with controlled lengths, ensuring even propagation delays across all interconnections without the timing issues associated with bond wire loop heights.
3Reliability
If bond wires with loop height control are used, then electrical connection is achieved, but manufacturing complexity increases
Solution Approach 1:
The invention removes bond wires and their associated loop height control requirements from the manufacturing process. The internal vertical interconnect structure is formed using standard semiconductor fabrication techniques integrated into the package substrate, significantly simplifying the manufacturing process while maintaining reliable electrical connections.
4Reliability
If traditional wire bonding is used, then interconnection is achieved, but package thickness increases
Solution Approach 1:
The patent transforms the interconnection approach from external horizontal wire bonding to internal vertical interconnect structures formed within the package substrate. This dimensional change allows electrical interconnection to be achieved with minimal impact on package thickness, as the interconnects are embedded within the substrate rather than adding external height.
Data Source
AI summary
A semiconductor wafer is made by forming a first conductive layer over a sacrificial substrate, mounting a semiconductor die to the sacrificial substrate, depositing an insulating layer over the semiconductor die and first conductive layer, exposing the first conductive layer and contact pad on the semiconductor die, forming a second conductive layer over the insulating layer between the first conductive layer and contact pad, forming solder bumps on the second conductive layer, depositing an encapsulant over the semiconductor die, first conductive layer, and interconnect structure, and removing the sacrificial substrate after forming the encapsulant to expose the conductive layer and semiconductor die. A portion of the encapsulant is removed to expose a portion of the solder bumps. The solder bumps are sized so that each extends the same outside the encapsulant. The semiconductor die are stacked by electrically connecting the solder bumps.