Internal Voltage Buffer Eliminates Dead Zone in Semiconductor Devices

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Solution Overview

Problem

Conventional internal voltage generation circuits in semiconductor devices suffer from a dead zone operating region, which slows down reaction speed and increases power consumption due to through current phenomena, especially when the voltage levels of pull-up and pull-down driving nodes overlap.

Innovation Solution

The design eliminates the dead zone by maintaining a voltage level difference between pull-up and pull-down driving nodes through a floating current source and current mirroring blocks, ensuring continuous operation and minimizing through current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional internal voltage generation circuit is used with separate reference voltages for pull-up and pull-down, then the circuit structure is simple, but a dead zone operating region occurs causing slow reaction speed and increased power consumption

Engineering Contradiction:
Improvereaction speedVSAvoidcircuit structure
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent changes the voltage parameter relationship between pull-up and pull-down driving nodes by maintaining a constant voltage level difference between them. This parameter change eliminates the dead zone operating region where both transistors are simultaneously off, thereby improving reaction speed without requiring fundamentally new circuit topology

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces a floating current source as an intermediary element that actively maintains the voltage level difference between pull-up and pull-down driving nodes. This mediator prevents the simultaneous cutoff of both transistors, eliminating the dead zone and improving response speed while adding controlled complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of energy

If conventional internal voltage generation circuit is used, then the circuit configuration is straightforward, but through current phenomena occur increasing power consumption

Engineering Contradiction:
Improvepower consumptionVSAvoidcircuit configuration
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent converts the potentially harmful through current phenomenon into a beneficial continuous operation mode. By maintaining a voltage level difference that keeps one transistor always conducting, the circuit eliminates the harmful simultaneous cutoff state, transforming the operating characteristics to reduce power consumption while ensuring continuous voltage regulation

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent ensures continuous useful action by maintaining a constant voltage level difference between pull-up and pull-down driving nodes, which guarantees that at least one transistor is always in conduction state. This continuous operation eliminates the dead zone and reduces power consumption while maintaining stable internal voltage generation

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS8766708B2Semiconductor device and operating method thereof
Publication Date: 2014.07.01 SK HYNIX INC
  • US8766708B2 patent drawing
  • US8766708B2 patent drawing
  • US8766708B2 patent drawing

AI summary

A semiconductor device includes an internal voltage input buffer configured to determine voltage levels of a pull-up driving node and a pull-down driving node as a result of a comparison between a voltage level of an internal voltage node and a voltage level of a reference voltage node such that the pull-up driving node and the pull-down driving node to maintain a voltage level difference, and an internal voltage driving block configured to pull-up drive the internal voltage node in response to the voltage level of the pull-up driving node and pull-down drive the internal voltage node in response to the voltage level of the pull-down driving node.